XRT8001 Datasheet, PDF (39/48 Pages) Exar Corporation – WAN Clock for T1 and E1 Systems

XRT8001
9.0 Generating a 1.544MHz clock signal via the
“CLK1/CLK2” outputs from either a 1.544MHz, or a
2.048MHz clock signal
When approaching this problem, be aware that the
XRT8001 WAN Clock can be configured to accept a
2.048MHz clock signal via the “FIN” input pin and
generate a 1.544MHz clock signal. However, the
XRT8001 WAN Clock cannot be configured to accept
a 1.544MHz clock signal, and generate a 1.544MHz
clock signal.
Also, note the XRT8001 WAN Clock can be configured
to accept a 2.048MHz clock signal (via the “FIN” input)
and generate a 1.544MHz clock signal if it configured
to operate in the “E1 to T1 Forward/Master” Mode. The
XRT8001 can similarly be configured to accept an
8kHz clock signal (via the same “FIN” input pin) and
generate a 1.544MHz clock signal if it is configured to
operate in the “Reverse/Slave” Mode.
Based upon these two points, the necessary circuitry
(in order to synthesize a 1.544MHz clock signal, from
either a 1.544MHz or a 2.048MHz clock signal) can be
achieved by the approach shown below in a block
diagram.
1.544MHz or 2.048MHz Clock Signal
2.048MHz or 8kHz Clock Signal
DDivividideebbyy
119933
8kHz
2 : 1 MUX
SESLLE
FIN
CLK1 1.544MHz
MSB
CLK2 1.544MHz
E1/T1* SELECT
XRT8001 WAN Clock
Figure 23: Synthesizing a 1.544MHz clock signal from a 1.544MHz or 2.048MHz clock
In Figure 23, the 1.544MHz or 2.048MHz input clock
signal is routed to two locations.
• One of the inputs of a “2:1 MUX”.
• The “CU” input of a “Divide-by-193” Block.
Figure 23 also includes a digital “E1/T1* SELECT”
signal. This signal is connected to both the “SEL” input
of the “2:1 MUX” and the “MSB” input of the XRT8001
WAN Clock. The basic idea behind this schematic is
as follows:
1. If the incoming clock signal (from the T1/E1 LIU for
example) is a 1.544MHz clock signal, then this signal
will be divided by 193. As it passes through the “Divide-
by-193” block a 8kHz clock signal is generated. This
8kHz clock signal will be applied to one of the inputs to
the “2:1 MUX”. (NOTE: A 1.544MHz clock signal is
applied to the other input to the “2:1 MUX”).
Rev. 1.01
In this case, the user must set the “E1/T1* SELECT”
signal to “LOW”, order to select “T1 rates” (1.544MHz).
By doing this, the 8kHz output from the “Divide-by-193”
block is selected and will be applied to the “FIN” input
of the XRT8001; and the XRT8001 will be configured to
operate in the “Slave” Mode.
At this point, the user will need to execute the appro-
priate steps in order to configure the XRT8001 into the
“Reverse-Slave” Mode.
2. If the incoming clock signal (from the T1/E1 LIU) is
a 2.048MHz clock signal, then this signal will also be
divided by 193. As it passes through the “Divide-by-
193” block, it generates a clock signal of a strange (and
undesirable frequency). This clock signal will be
applied to one of the inputs to the “2:1 MUX” (NOTE:
The 2.048MHz clock will also be applied to the other
input of the “2:1 MUX).
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