XRT8001 Datasheet, PDF (41/48 Pages) Exar Corporation – WAN Clock for T1 and E1 Systems

XRT8001
NOTE: In order to synthesize and output a clock signal via
the “CLK1” output pin, the user must write a “1” into the D0
(PL1EN) bit-field within Command Register, CR0, as indi-
cated above.
This step configures the XRT8001 WAN to operate in
the “E1 to T1 Forward/Master” Mode. In this mode, the
XRT8001 WAN Clock will be configured to accept a “Q
x 2.048MHz” clock signal via the “FIN” input and will
synthesize a 1.544MHz clock signal via both the
“CLK1” and “CLK2” output pins.
STEP 3 – Next specify the value for “Q” (e.g., as in “Q
x 2.048MHz” clock signal, which will be applied to the
“FIN” input).
In this application, the value for “Q” is “1”. Hence, the
user must configure the XRT8001 WAN Clock to use
this value for “Q”, by writing the binary value for “Q – 1”
into Command Register, CR1. In this application, the
user should write “0000” into the Command Register,
as indicated below.
Command Register, CR1 (Address = 0x01)
D4
D3
D2
D1
D0
M4
M3
M2
M1 PL2EN
0
0
0
0
1
NOTE: In order to synthesize and output a clock signal via
the “CLK2” output pin, the user must write a “1” into the “D0
(PL2EN) bit-field within Command Register, CR1, as indi-
cated above.
STEP 4 – Write the binary value “11111” into both
Command Registers CR2 and CR3. This is necessary
in order to ensure proper operation of the XRT8001
WAN Clock.
STEP 5 – Enable the desired output signals: SYNC,
CLK1, CLK2, and LOCKDET. This is accomplished by
writing a “1” into the corresponding bit-field, within
Command Register, CR4, as illustrated below.
Command Register, CR4 (Address = 0x04)
D4
D3
D2
D1
D0
SYNCEN CLK1EN CLK2EN LDETDIS2 LDETDIS1
1
1
1
1
1
Once the user has executed these five steps, then the
circuitry (in Figure 6) is now configured to accept a
2.048MHz clock signal (from the T1/E1 LIU) and
synthesize a 1.544MHz clock signal.
Configuring the Circuitry in Figure 24 to accept a
1.544MHz clock signal and synthesize a 1.544MHz
clock signal.
The user can configure the circuitry (within Figure 6) to
accept a 1.544MHz clock signal, and synthesize a
1.544MHz clock signal, by executing the following four
(4) steps.
STEP 1 – Drive the “E1/T1* SELECT” input pin to
“LOW”. This step configures the “2:1 MUX” to select
and apply the 8kHz clock signal to the “FIN” input of the
XRT8001 WAN Clock, and configures the XRT8001
WAN Clock into the “Slave” Mode.
NOTE: The next few steps will be devoted to configuring
the XRT8001 WAN Clock into the “Reverse/Slave” Mode.
STEP 2 – Write the binary value “1000” into Command
Register CR0, within the XRT8001 WAN Clock, as
indicated below.
Command Register, CR0 (Address = 0x00)
D4
D3
D2
D1
D0
IOC4 IOC3
IOC2 IOC1 PL1EN
1
0
0
0
1
NOTE: In order to synthesize and output a clock signal via
the “CLK1” output pin, the user must write a “1” into the “D0
(PL1EN) bit-field within Command Register, CR0, as indi-
cated above.
This step configures the XRT8001 WAN to operate in
the “Reverse/Slave” Mode. In this mode, the XRT8001
WAN Clock will be configured to accept an 8kHz clock
signal via the “FIN” input and will synthesize a
1.544MHz clock signal via both the “CLK1” and “CLK2”
output pins.
STEP 3 – Write the binary expression “0000” into bit-
fields D4 through D1, within Command Register CR1,
as illustrated below.
Rev. 1.01
41