XRT8001 Datasheet, PDF (34/48 Pages) Exar Corporation – WAN Clock for T1 and E1 Systems

XRT8001
Values written into
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Value for K
“SEL1[4:0]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CLK1/CLK2
(K x 56kHz)
56kHz
112kHz
168kHz
224kHz
280kHz
336kHz
392kHz
448kHz
504kHz
560kHz
616kHz
672kHz
728kHz
784kHz
840kHz
896kHz
952kHz
1.008MHz
1.064MHz
1.120MHz
1.176MHz
1.232MHz
1.288MHz
1.344MHz
1.400MHz
1.456MHz
1.512MHz
1.568MHz
1.624MHz
1.680MHz
1.756MHz
1.812MHz
T (ns)
Output Frequency
376
376
376
376
450
376
323
283
500
450
410
376
347
323
302
283
529
500
474
450
429
410
392
376
361
347
335
323
312
302
292
283
Table 10: Timing Relationship (T), from the rising edge of “CLK1/CLK2” to the rising edge of “FIN”
with the XRT8001 in Slave Mode, and FIN = 8kHz
6.12 Master Mode:
If the XRT8001 is operating in the “Master” Mode, then
the timing relationship between the “Reference signal”
(e.g., a signal applied to the “FIN” and the “CLK1” or
“CLK2” output is not readily available. This is because
the “FIN” signal is internally divided down, via a
Programmable Divider, which generates the “SYNC”
signal. The internal Phase Locked Loops (within the
XRT8001) are “locked” onto the “SYNC” signal. Hence,
there is definitely a phase relationship between the
“SYNC” and the “CLK1, CLK2” outputs.
Rev. 1.01
34