45111 Datasheet, PDF (97/184 Pages) List of Unclassifed Manufacturers – 14-DAY MONEY BACK GUARANTEE

10 SX Special Features and Coding Tips
The block diagram in Figure 16 – SX48/52 Multi-Function Timers, below, shows the components of one
timer:
Figure 16 - SX48/52 Multi-Function Timers
Capture 2 (RB5/RC1)
System Clock
16-Bit Comparison R2
or Capture Register (2)
Compare
Interrupt
16-Bit Comparison Register
R1
Output (RB6/RC2)
8-Bit Prescaler
16-Bit Comparator
External Clock
(RB7/RC3)
Multiplexer
Capture 1 (RB4/RC0)
16-Bit Counter
16-Bit Capture Register (1)
Capture
Interrup
t
Registers R1, R2 and the capture registers can be accessed by mov !rb, w (Timer1), or mov !rc, w
(Timer2) instructions. The remaining registers cannot be accessed via software.
Timer 1 shares its input and output lines with the Port B pins 4...7, and Timer 2 shares its input and
output lines with the Port C pins 0...3. If a timer is active, those pins can no longer used for "regular"
I/O purposes.
10.3.1 PWM Mode
In this mode, the timer generates a square wave signal with programmable frequency, and duty cycle.
For this purpose, the contents of the two comparison registers determine for how long the signal is high,
and low.
The 16-bit counter starts with a value of 0, and keeps incrementing until it has reached the value of R1.
Then, the counter is reset to 0, the output is toggled, and (if enabled) an interrupt is generated.
Next, the counter keeps incrementing until it reaches the value of R2. Again, the counter is reset to 0, the
output signal is toggled, and an interrupt is triggered (if enabled).
These two steps are repeated continuously. The contents of R1 and R2 determine the frequency and the
duty cycle of the generated output signal. When R1 and R2 contain the same value, a square wave with
a duty cycle of 50% is generated. In order to generate a signal with a constant frequency, and a varying
SX-Key/Blitz Development System Manual 2.0 • Parallax, Inc. • Page 97