45111 Datasheet, PDF (95/184 Pages) List of Unclassifed Manufacturers – 14-DAY MONEY BACK GUARANTEE

10 SX Special Features and Coding Tips
The following are points to remember with Wake-Up Interrupts:
• The interrupt routine must be located starting at address $0 in the SX program.
• It is up to the SX program to clear the bits of the Pending register when future interrupts on that pin
are desired. This should normally be done as part of the interrupt routine. The MOV !rb,
#%00000000 instruction effectively clears all bits of the Pending register at the same time that it
stores the current edge detection status in W.
• The SX chip will activate the interrupt routine exactly 5 clock cycles in Turbo mode or exactly 10
clock cycles in compatible mode after a Wake-Up Edge Detection event occurs. This deterministic
feature allows for nearly jitter-free interrupt response. Latency may vary by as much as +1
instruction cycle when interrupting on external asynchronous events, thus a high clock speed may
be necessary to lessen the effects.
• If multiple interrupt pins are required, the SX chip may not be able to properly process them in
certain situations. See Interrupts, below, for more information.
• An edge-detection interrupt event will wake up the SX chip from a SLEEP mode.
10.2.7 Comparator
I/O pins 0 through 2 in port B can be set for comparator operation. This can be configured by writing to
the EN and OE bits of the Comparator register (CMP_B) and monitored by reading the RES bit. The
comparator mode is disabled by default. Comparator mode can be activated for all three pins,
regardless of pin direction, but really matters only when pin 1 and 2 are set to input mode (pin 0 can
optionally be set to output the comparative result). By configuring Comparator mode, the SX chip can
quickly determine logical differences between two signals and even indicate those differences for
external circuitry.
When comparator mode is activated, the RES bit in the Comparator register indicates the result of the
compare. A high bit (1) indicates the voltage on pin 2 is higher than that of pin 1, a low bit (0) indicates
the voltage on pin 2 is lower than that of pin 1. If the OE bit (Output Enable) of the Comparator register
is cleared, output pin 0 of port B reflects the state of the RES bit.
To configure port B I/O pins 0 though 2 for Comparator mode:
1) Set the MODE register to $08 (the value for Comparator register configuration).
2) Use the port configuration instruction to enable the Comparator and, optionally, the result output
on pin 0.
3) Set I/O pin directions appropriately.
The following code snippet demonstrates this:
SX-Key/Blitz Development System Manual 2.0 • Parallax, Inc. • Page 95