45111 Datasheet, PDF (155/184 Pages) List of Unclassifed Manufacturers – 14-DAY MONEY BACK GUARANTEE

15 Appendix E: SX Data Sheet
Bit 1:
Digit Carry (DC)
After an addition:
Set (1) = a carry from bit 4 has occurred
Clear (0) = no carry from bit 4 has occurred
After a subtraction:
Set (1) = no borrow from bit 4 has occurred
Clear (0) = a borrow from bit 4 has occurred
Bit 0:
Carry (C)
After an addition:
Set (1) = a carry has occurred
Clear (0) = no carry has occurred
After a subtraction:
Set (1) = no borrow has occurred
Clear (0) = a borrow has occurred
The Carry flag also serves as the ninth bit in RL and RR instructions. We can examine the operation of
each of these instructions to further clarify the behavior of the carry flag. Consider the RR instruction
first. When an RR instruction is performed on a RAM byte, the data in the RAM byte is rotated through
the carry flag.
Figure 23 - Rotate Right
C
76543210
Similarly, when an RL instruction is performed on a RAM byte, the data in the RAM byte is rotated
through the carry flag.
Figure 24 - Rotate Left
C
76543210
15.2.9 The FSR – File Select Register ($04)
The SX chip utilizes 12-bit op-codes. Instructions that specify a register as an operand can only express
5-bits of the register address. This means that only registers from $00 up to $1F can be accessed. The File
Select Register (FSR) along with the 5-bit register operand is used to provide the ability to access
registers beyond $1F. Figure 25 – Global Register Addressing SX20/28/48/52 (direct) shows how the
FSR’s upper three bits select one of eight RAM banks on the SX20/28. Figure 26 – SX20/28 General
Purpose Register Addressing (direct) shows how the FSR’s upper four bits select one of sixteen RAM
banks on the SX48/52.
SX-Key/Blitz Development System Manual 2.0 • Parallax, Inc. • Page 155