45111 Datasheet, PDF (109/184 Pages) List of Unclassifed Manufacturers – 14-DAY MONEY BACK GUARANTEE

11 Appendix A: SX Features
11 Appendix A: SX Features
11.1 Introduction
The SX chip is a fully static CMOS MPU conservatively rated for DC to 50 (or 75) MHz operation. The
SX provides 2K words of on-chip E²Flash program memory (4K words in SX48/52). In Turbo mode, all
instructions are single cycle except program branches, which take three cycles, and IREAD, which takes
four cycles.
11.2 CPU Features
• Single cycle instruction execution (20 ns cycle time @ 50 MHz, 13.3 ns @ 75 MHz)
• DC to 50 MHz operation (75 MHz on selected chips)
• User selectable clock options: (Internal R/C, External R/C, resonator, crystal oscillator or crystal-
oscillator pack)
• Internal R/C oscillator (31 KHz to 4 MHz, +/- 8% accuracy)
• 43 single-word basic instructions
• 2048 x 12-bits (4096 x 12-bits in SX48/52) E²Flash program memory rated for 10,000 rewrite cycles
• Up to 137 bytes (262 bytes in SX48/52) of directly, or indirectly, addressable RAM
• Selectable 8-level hardware stack
• Fixed interrupt response time: 60 ns internal, 100 ns external
• Hardware context save/restore of PC, W, STATUS, and FSR on interrupt.
• Multi-Input Wake-Up (MIWU) on 8 pins
• In-system programming via OSC pins
• Single-step and breakpoint debugging via OSC2 pin
• Analog comparator (RB0 out, RB1 in-, RB2 in+)
• Built-in brown-out detector (On/Off, 4.2V) (4.2, 2.6, 2.2, Off in SX48/52)
• W mappable into RTCC space for flexibility
• Nine sources of interrupts (17 in SX48/52)
• 1998 UL compliance and fast lookup provided through run-time readable code
11.3 Peripheral and I/O Features
• Every pin programmable as input or output
• Inputs are each TTL or CMOS level selectable
• All pins include selectable internal pull-ups (~20 kΩ to V_DD)
• RB, RC, RD and RE inputs each selectable as Schmitt Trigger
SX-Key/Blitz Development System Manual 2.0 • Parallax, Inc. • Page 109