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15 Appendix E: SX Data Sheet
15.3.2 Port B Registers
There are eight registers used to configure the I/O pins of Port B. The TRIS_B register configures the
data direction of the Port B pins as input or output. The LVL_B register configures the input pins as TTL
or CMOS voltage level. The PLP_B register enables/disables pull up resistors on Port B input pins. The
ST_B register enables/disables the Schmitt-Trigger inputs on Port B input pins. The WKEN_B register
enables/disables the multi-input wake up for interrupts on Port B input pins. The WKED_B register
selects rising/falling edge detection on Port B input pins. The WKPND_B register contains the state of
the MIWU pins. The CMP_B registers configures and provides the results from the comparator pins. To
access these registers you must first write a particular value to the MODE register. Please refer to Table
32 – SX20/28 Mode Register to find the values required in the MODE register to access the Port B
Registers. Note: All the bits in the following registers are set to ‘1’ on power up.
15.3.2.1 TRIS_B – Data Direction Register
TRIS_B
76543210
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
A bit set to ‘1’ in this register sets the corresponding I/O port pin to input (high z) mode.
A bit set to ‘0’ in this register sets the corresponding I/O port pin to output mode.
15.3.2.2 LVL_B - TTL/CMOS Select Register
LVL_B
76543210
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
A bit set to ‘1’ in this register sets the input level of the corresponding port pin to TTL.
A bit set to ‘0’ in this register sets the input level of the corresponding port pin to CMOS.
15.3.2.3 PLP_B – Pull-Up Resistor Enable Register
PLP_B
76543210
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
A bit set to ‘1’ in this register disables the weak pull-up resistor on the corresponding port pin. A bit set
to ‘0’ in this register enables the weak pull-up resistor on the corresponding port pin.
Page 168 • SX-Key/Blitz Development System Manual 2.0 • Parallax, Inc.