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15 Appendix E: SX Data Sheet
15.4.2 Mode register (SX48/52)
Similar to the SX20/28, instructions like mov !ra, w are used to access the control registers with the
MODE register previously set to a value to select the correct register type. Table 33 - SX48/52 Mode
Register, shows the possible values for the MODE register. The gray areas are undefined.
Table 33 - SX48/52 Mode Register
SX48/52 MODE (m) Register and mov !r?, w
m
mov !ra, w
mov !rb, w
mov !rc, w
mov !rd, w
mov !re, w
$00
read T1CPL
read T2PL
$01
read T1CPH
read T2CPH
$02
read T1R2CML
read T2R2CML
$03
read T1R2CMH
read T2R2CMH
$04
read T1R1CML
read T2R1CML
$05
read T1R1CMH
read T2R1CMH
$06
read T1CNTB
read T2CNTB
$07
read T1CNTA
read T2CNTA
$08
exchange CMP_B
$09
exchange WKPND_B
$0a
write WKED_B
$0b
write WKEN_B
$0c
read ST_B
read ST_C
read ST_D
read ST_E
$0d read LVL_A
read LVL_B
read LVL_C
read LVL_D
read LVL_E
$0e read PLP_A
read PLP_B
read PLP_C
read PLP_D
read PLP_E
$0f read TRIS_A
read TRIS_B
read TRIS_C
read TRIS_D
read TRIS_E
$10
clear Timer 1
clear Timer 2
$11
$12
write T1R2CML
write T2R2CML
$13
write T1R2CMH
write T2R2CMH
$14
write T1R1CML
write T2R1CML
$15
write T1R1CMH
write T2R1CMH
$16
write T1CNTB
write T2CNTB
$17
write T1CNTA
write T2CNTA
$18
exchange CMP_B
$19
exchange WKPND_B
$1a
write WKED_B
$1b
write WKEN_B
$1c
write ST_B
write ST_C
write ST_D
write ST_E
$1d write LVL_A
write LVL_B
write LVL_C
write LVL_D
write LVL_E
$1e write PLP_A
write PLP_B
write PLP_C
write PLP_D
write PLP_E
$1f write TRIS_A
write TRIS_B
write TRIS_C
write TRIS_D
write TRIS_E
Abbreviations: T1CPH, T2CPH: Timer 1/2 capture, high byte. T1CPL, T2CPL: Timer 1/2 capture, low byte.
T1R1CMH, T2R1CMH: Timer 1/2 register R1, high byte. T1R1CML, T2R1CML: Timer 1/2 register R1, low
byte. T1R2CMH, T2R2CMH: Timer 1/2 register R2, high byte. T1R2CML, T2R2CML: Timer 1/2 register R2,
low byte.
SX-Key/Blitz Development System Manual 2.0 • Parallax, Inc. • Page 173