45111 Datasheet, PDF (91/184 Pages) List of Unclassifed Manufacturers – 14-DAY MONEY BACK GUARANTEE

10 SX Special Features and Coding Tips
The following code snippet demonstrates this:
; Logic Level Configuration
;
MODE $0D
; Set Mode to Logic Level configuration
MOV !ra,#%0000
; Port A bits 0-3 to CMOS
MOV !rb,#%11110000 ; Port B bits 4-7 to TTL, bits 0-3 CMOS
MOV !rc,#%00001111 ; Port C bits 4-7 to CMOS, bits 0-3 TTL
MODE $0F
; Set Mode to allow Direction configuration
MOV !ra,#%1100
; Port A bits 0-1 to output, bits 2-3 input
MOV !rb,#%10110011 ; Port B bits 2,3,6 to output, all others input
MOV !rc,#%11011110 ; Port C bits 0,5 to output, all others input
10.2.4 Schmitt-Trigger
Every I/O pin in port B through port E can be set to normal or Schmitt-Trigger input. This can be
configured by writing to the appropriate Schmitt-Trigger register (ST_B, ST_C, ST_D and ST_E). The
I/O pins are set to normal input mode by default. Schmitt-Trigger mode can be activated for all pins,
regardless of pin direction but really matter only when the associated pin is set to input mode. By
configuring Schmitt-Trigger mode on input pins, the SX chip can be less sensitive to minor noise on the
input pins. , below, details the characteristics of Schmitt-Trigger inputs.
Figure 15 - Schmitt Trigger Characteristics
Schmitt-Trigger inputs are conditioned with a large area of hysteresis. The threshold for a logic 0 is 15%
of Vdd and the threshold for a logic 1 is 85% of Vdd. The input pin defaults to an unknown state until
the initial voltage crosses a logic 0 or logic 1 boundary. A voltage must cross above 85% of Vdd to be
interpreted as a logic 1 and must cross below 15% of Vdd to be interpreted as a logic 0. If the voltage
transitions somewhere between the two thresholds, the interpreted logic state remains the same as the
previous state.
SX-Key/Blitz Development System Manual 2.0 • Parallax, Inc. • Page 91