45111 Datasheet, PDF (90/184 Pages) List of Unclassifed Manufacturers – 14-DAY MONEY BACK GUARANTEE

10 SX Special Features and Coding Tips
10.2.3 Logic Level
Every I/O pin has selectable logic level control that determines the voltage threshold for a logic level 0
or 1. The default logic level for all I/O pins is TTL but can be modified by writing to the appropriate
logic-level register (LVL_A, LVL_B, LVL_C, LVL_D and LVL_E). The logic level can be configured for
all pins, regardless of pin direction, but really matters only when the associated pin is set to input mode.
By configuring logic levels on input pins, the SX chip can be sensitive to both TTL and CMOS logic
thresholds. Figure 14 – TTL and CMOS Levels, below, demonstrates the difference between TTL and
CMOS logic levels.
Figure 14 - TTL and CMOS Levels
The logic threshold for TTL is 1.4 volts; a voltage below 1.4 is considered to be a logic 0, while a voltage
above is considered to be a logic 1. The logic threshold for CMOS is 50% of Vdd, a voltage below ½ Vdd
is considered to be a logic 0, while a voltage above ½ Vdd is considered to be a logic 1.
To configure the I/O pins to use CMOS- or TTL-level logic:
1) Set the MODE register to $0D (the value for logic-level register configuration).
2) Use the port configuration instruction to set the individual logic-level state of each I/O pin within
each port. A high bit (1) sets the corresponding pin to TTL-level logic and a low bit (0) sets it to
CMOS-level logic.
3) Set I/O pin directions as necessary.
Page 90 • SX-Key/Blitz Development System Manual 2.0 • Parallax, Inc.