45111 Datasheet, PDF (167/184 Pages) List of Unclassifed Manufacturers – 14-DAY MONEY BACK GUARANTEE

15 Appendix E: SX Data Sheet
stack and the special shadow registers for W, STATUS, and the FSR, which were preserved during
interrupt handling. RETIW behaves the same as RETI but also compensates the RTCC by adding the
value in W to the RTCC.
15.3 Port Configuration Registers
15.3.1 Port A Registers
There are three registers used to configure the I/O pins of Port A. The TRIS_A register configures the
data direction of the Port A pins as input or output. The LVL_A register configures the input pins as
TTL or CMOS voltage level. The PLP_A register enables/disables pull up resistors on Port A input pins.
To access these registers you must first write a particular value to the MODE register. Please refer
toTable 32 – SX20/28 Mode Register to find the values required in the MODE register to access the
following Port A Registers. Note: All the bits in the following registers are set to ‘1’ on power up.
15.3.1.1 TRIS_A – Data Direction Register
TRIS_A
76543210
- - - - RA3 RA2 RA1 RA0
A bit set to ‘1’ in this register sets the corresponding I/O port pin to input (high z) mode.
A bit set to ‘0’ in this register sets the corresponding I/O port pin to output mode.
15.3.1.2 LVL_A - TTL/CMOS Select Register
LVL_A
76543210
- - - - RA3 RA2 RA1 RA0
A bit set to ‘1’ in this register sets the input level of the corresponding port pin to TTL.
A bit set to ‘0’ in this register sets the input level of the corresponding port pin to CMOS.
15.3.1.3 PLP_A – Pull-Up Resistor Enable Register
PLP_A
76543210
- - - - RA3 RA2 RA1 RA0
A bit set to ‘1’ in this register disables the weak pull-up resistor on the corresponding port pin. A bit set
to ‘0’ in this register enables the weak pull-up resistor on the corresponding port pin.
SX-Key/Blitz Development System Manual 2.0 • Parallax, Inc. • Page 167