W5500 Datasheet, PDF (62/65 Pages) List of Unclassifed Manufacturers – Supports 8 independent sockets simultaneously

5.5.4 SPI Timing
SCSn
V_IH
V_IL
TCSS
SCLK
V_IH
V_IL
MOSI
V_IH
V_IL
V_OH
MISO _VOL
HI-Z
TWH
TWL
TDS TDH
TOV
TCS
TCSH
TOH
TCHZ
HI-Z
Figure 23. SPI Timing
Symbol
F_SCK
T_WH
T_WL
T_CS
T_CSS
T_CSH
T_DS
T_DH
T_OV
T_OH
T_CHZ
Description
SCK Clock Frequency
SCK High Time
SCK Low Time
SCSn High Time
SCSn Setup Time
SCSn Hold Time
Data In Setup Time
Data In Hold Time
Output Valid Time
Output Hold Time
SCSn High to Output Hi-Z
Min
Max
80/33.3⁴
6
6
30
5
-
5
3
3
5
0
2.1⁵
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4 _{Theoretical Guaranteed Speed}
Even though theoretical design speed is 80MHz, the signal in the high speed may be distorted because
of the circuit crosstalk and the length of the signal line. The minimum guaranteed speed of the SCLK
is 33.3 MHz which was tested and measured with the stable waveform.
Please refer to the SPI Application Note which shows the WIZnet test environment and results.
5 _{2.1ns is when pn loaded with 30pF. The time is shorter with lower capacitance.}
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W5500 Datasheet Version1.0 (August 2013)