W5500 Datasheet, PDF (29/65 Pages) List of Unclassifed Manufacturers – Supports 8 independent sockets simultaneously

3.1
Common Register Block
Common Register Block configures the general information of W5500 such as IP and
MAC address. This block can be selected by the BSB[4:0] value of SPI Frame. <Table
3> defines the offset address of registers in this block. Refer to „Chapter 4.1‟ for
more details about each register.
Table 3. Offset Address for Common Register
Offset
0x0000
Mode
(MR)
Register
0x0001
0x0002
0x0003
0x0004
Gateway Address
(GAR0)
(GAR1)
(GAR2)
(GAR3)
0x0005
0x0006
0x0007
0x0008
Subnet Mask Address
(SUBR0)
(SUBR1)
(SUBR2)
(SUBR3)
Source Hardware Address
0x0009 (SHAR0)
0x000A (SHAR1)
0x000B (SHAR2)
0x000C (SHAR3)
0x000D (SHAR4)
0x000E (SHAR5)
0x000F
0x0010
0x0011
0x0012
Source IP Address
(SIPR0)
(SIPR1)
(SIPR2)
(SIPR3)
0x003A ~ 0xFFFF
Offset
0x0013
0x0014
Register
Interrupt Low Level Timer
(INTLEVEL0)
(INTLEVEL1)
Offset
0x0021
0x0022
0x0023
Register
(PHAR3)
(PHAR4)
(PHAR5)
Interrupt
0x0015 (IR)
Interrupt Mask
0x0016 (IMR)
Socket Interrupt
0x0017 (SIR)
PPP Session Identification
0x0024 (PSID0)
0x0025 (PSID1)
PPP Maximum Segment Size
0x0026 (PMRU0)
0x0027 (PMRU1)
Socket Interrupt Mask
0x0018 (SIMR)
Retry Time
0x0019 (RTR0)
0x001A (RTR1)
Unreachable IP address
0x0028 (UIPR0)
0x0029 (UIPR1)
0x002A (UIPR2)
0x002B (UIPR3)
Retry Count
Unreachable Port
0x001B (RCR)
0x002C (UPORTR0)
PPP LCP Request Timer
0x002D (UPORTR1)
0x001C (PTIMER)
PHY Configuration
PPP LCP Magic number
0x002E (PHYCFGR)
0x001D (PMAGIC)
0x002F
PPP Destination MAC Address
~
Reserved
0x001E (PHAR0)
0x0038
0x001F (PHAR1)
Chip version
0x0020 (PHAR2)
0x0039 (VERSIONR)
Reserved
W5500 Datasheet Version1.0 (August 2013)
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