W5500 Datasheet, PDF (13/65 Pages) List of Unclassifed Manufacturers – Supports 8 independent sockets simultaneously

The W5500 supports SPI Mode 0 and Mode 3. Both MOSI and MISO signals use
transfer sequence from Most Significant Bit (MSB) to Least Significant Bit (LSB) when
MOSI signal transmits and MISO signal receives. MOSI & MISO signals always transmit
or receive in sequence from the Most Significant Bit (MSB) to Least Significant Bit
(LSB).
Sampling Toggling
SCLK
SCLK
Toggling Sampling
MISO/MOSI
MISO/MOSI
Mode 0 : SCLK idle level low
Figure 6. SPI Mode 0 & 3
Mode 3 : SCLK idle level high
2.1
SPI Operation Mode
W5500 is controlled by SPI Frame (Refer to the Chapter 2.2 SPI Frame) which
communicates with the External Host. W5500 SPI Frame consists 3 phases, Address
Phase, Control Phase and Data Phase.
Address Phase specifies 16 bits Offset Address for W5500 Register or TX/RX Memory.
Control Phase specifies the block to which Offset (set by Address Phase) belongs, and
specifies Read/Write Access Mode and SPI Operation Mode (Variable Length Data /
Fixed Length Data Mode).
And Data Phase specifies random length (N-bytes, 1 ≤ N) Data or 1 byte, 2 bytes and
4 bytes Data.
If SPI Operation Mode is set as Variable Length Data Mode (VDM), SPI Bus Signal SCSn
must be controlled by the External Host with SPI Frame step.
At the Variable Length Data Mode, SCSn Control Start (Assert (High-to-Low)) informs
W5500 of SPI Frame Start (Address Phase), and SCSn Control End (De-assert (Low-to-
High) informs W5500 of SPI Frame End (Data Phase End of random N byte).
W5500 Datasheet Version1.0 (August 2013)
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