W5500 Datasheet, PDF (18/65 Pages) List of Unclassifed Manufacturers – Supports 8 independent sockets simultaneously

2.3.1 Write Access in VDM
SPI Frame Start
SCSn
SCSn shoud be remained low until SPI Frame Transmit done.
MODE3
SCLK MODE0
MOSI
012
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
16 bits Offset Address
BSB[4:0]
RWB OM[1:0]
8-bit Data 1
15 14 13
3 2 1 0 4 3 2 1 0_{W 00} 7 6 5 4 3 2 1 0
MISO
SCSn
SCLK
MOSI
MISO
SCSn Should be remained low until SPI Frame Transmit done.
32 33 34 35 36 37 37 39
...
8N + 16
SPI Frame End
8N + 24
8-bit Data 2
...
8-bit Data N
7 6 5 4321 0 7 6 5 4321 07 6 5 432 10
Figure 8. Write SPI Frame in VDM mode
Figure 8 shows the SPI Frame when the external host accesses W5500 for writing.
In VDM mode, the RWB signal is „1‟ (Write), OM[1:0] is „00‟ in SPI Frame Control
Phase.
At this time the External Host assert (High-to-Low) SCSn signal before
transmitting SPI Frame.
Then the Host transmits SPI Frame‟s all bits to W5500 through MOSI signal. All
bits are synchronized with the falling edge of the SCLK.
After finishing the SPI Frame transmit, the Host deasserts SCSn signal (Low-to-
High).
When SCSn is Low and the Data Phase continues, the Sequential Data Write can
be supported.
18 / 65
W5500 Datasheet Version1.0 (August 2013)