W5500 Datasheet, PDF (42/65 Pages) List of Unclassifed Manufacturers – Supports 8 independent sockets simultaneously

PHYCFGR (W5500 PHY Configuration Register) [R/W] [0x002E] [0b10111XXX]
PHYCFGR configures PHY operation mode and resets PHY. In addition, PHYCFGR
indicates the status of PHY such as duplex, Speed, Link.
Bit
Symbol
Description
Reset [R/W]
7
RST
When this bit is ‘0’, internal PHY is reset.
After PHY reset, it should be set as ‘1’.
Configure PHY Operation Mode
1: Configure with OPMDC[2:0] in PHYCFGR
0: Configure with the H/W PINs(PMODE[2:0])
This bit configures PHY operation mode with OPMDC[2:0] bits or
PMODE[2:0] PINs. When W5500 is reset by POR or RSTn PIN, PHY
6
OPMD
operation mode is configured with PMODE[2:0] PINs by default. After
POR or RSTn reset, user can re-configure PHY operation mode with
OPMDC[2:0]. If user wants to re-configure with PMDC[2:0], it should
reset PHY by setting the RST bit to ‘0’ after the user configures this
bit as ‘1’ and OPMDC[2:0] .
Operation Mode Configuration Bit[R/W]
These bits select the operation mode of PHY such as following table.
543
Description
0 0 0 10BT Half-duplex, Auto-negotiation disabled
0 0 1 10BT Full-duplex, Auto-negotiation disabled
5~3
OPMDC
0 1 0 100BT Half-duplex, Auto-negotiation disabled
0 1 1 100BT Full-duplex, Auto-negotiation disabled
1 0 0 100BT Half-duplex, Auto-negotiation enabled
1 0 1 Not used
1 1 0 Power Down mode
1 1 1 All capable, Auto-negotiation enabled
2
DPX
Duplex Status [Read Only]
1: Full duplex
0: Half duplex
1
SPD
Speed Status [Read Only]
1: 100Mpbs based
0: 10Mpbs based
0
LNK
Link Status [Read Only]
1: Link up
0: Link down
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W5500 Datasheet Version1.0 (August 2013)