W5500 Datasheet, PDF (15/65 Pages) List of Unclassifed Manufacturers – Supports 8 independent sockets simultaneously

2.2.2
Control Phase
The Control Phase specifies the Block to which the Offset Address (set by Address
Phase) belongs, the Read/Write Access Mode and the SPI Operation Mode.
7
BSB4
6
BSB3
5
BSB2
4
BSB1
3
BSB0
2
1
0
RWB OM1 OM0
Bit
Symbol
Description
Block Select Bits
W5500 has Common Register, 8 Socket Register, TX/RX Buffer Block
for each Socket.
The next table shows the Block selected by BSB[4:0].
7~3 BSB [4:0]
BSB [4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
W5500 Datasheet Version1.0 (August 2013)
Meaning
Selects Common Register.
Selects Socket 0 Register
Selects Socket 0 TX Buffer
Selects Socket 0 RX Buffer
Reserved
Selects Socket 1 Register
Selects Socket 1 TX Buffer
Selects Socket 1 RX Buffer
Reserved
Selects Socket 2 Register
Selects Socket 2 TX Buffer
Selects Socket 2 RX Buffer
Reserved
Selects Socket 3 Register
Selects Socket 3 TX Buffer
Selects Socket 3 RX Buffer
Reserved
Selects Socket 4 Register
Selects Socket 4 TX Buffer
Selects Socket 4 RX Buffer
Reserved
Selects Socket 5 Register
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