W5500 Datasheet, PDF (2/65 Pages) List of Unclassifed Manufacturers – Supports 8 independent sockets simultaneously

W5500
The W5500 chip is a Hardwired TCP/IP embedded Ethernet controller that provides
easier Internet connection to embedded systems. W5500 enables users to have the
Internet connectivity in their applications just by using the single chip in which
TCP/IP stack, 10/100 Ethernet MAC and PHY embedded.
WIZnet„s Hardwired TCP/IP is the market-proven technology that supports TCP, UDP,
IPv4, ICMP, ARP, IGMP, and PPPoE protocols. W5500 embeds the 32Kbyte internal
memory buffer for the Ethernet packet processing. If you use W5500, you can
implement the Ethernet application just by adding the simple socket program. It‟s
faster and easier way rather than using any other Embedded Ethernet solution. Users
can use 8 independent hardware sockets simultaneously.
SPI (Serial Peripheral Interface) is provided for easy integration with the external
MCU. The W5500‟s SPI supports 80 MHz speed and new efficient SPI protocol for the
high speed network communication. In order to reduce power consumption of the
system, W5500 provides WOL (Wake on LAN) and power down mode.
Features
- Supports Hardwired TCP/IP Protocols : TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE
- Supports 8 independent sockets simultaneously
- Supports Power down mode
- Supports Wake on LAN over UDP
- Supports High Speed Serial Peripheral Interface(SPI MODE 0, 3)
- Internal 32Kbytes Memory for TX/RX Buffers
- 10BaseT/100BaseTX Ethernet PHY embedded
- Supports Auto Negotiation (Full and half duplex, 10 and 100-based )
- Not supports IP Fragmentation
- 3.3V operation with 5V I/O signal tolerance
- LED outputs (Full/Half duplex, Link, Speed, Active)
- 48 Pin LQFP Lead-Free Package (7x7mm, 0.5mm pitch)
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W5500 Datasheet Version1.0 (August 2013)