W5500 Datasheet, PDF (22/65 Pages) List of Unclassifed Manufacturers – Supports 8 independent sockets simultaneously

1 Byte READ Access Example
When the Host reads the „Socket Status Register(S7_SR) of the Socket 7‟s Register
Block by using VDM mode, the data is read with the SPI Frame below. Let‟s S7_SR to
„SOCK_ESTABLISHED (0x17)‟.
Offset Address = 0x0003
BSB[4:0]
= ‘11101’
RWB
= ‘0’
OM[1:0]
1^st Data
= ‘00’
= 0x17
The External Host asserts (High-to-Low) SCSn signal before transmitting SPI Frame,
then the Host transmits Address and Control Phase to W5500 through the MOSI signal.
Then the Host receives Data Phase from the MISO signal.
After finishing the Data Phase receives, the Host deasserts SCSn signal (Low-to-
High). (Refer to the Figure 12.)
SCSn
Figure 12. S7_SR Read in VDM Mode
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W5500 Datasheet Version1.0 (August 2013)