W5500 Datasheet, PDF (34/65 Pages) List of Unclassifed Manufacturers – Supports 8 independent sockets simultaneously

INTLEVEL (Interrupt Low Level Timer Register) [R/W] [0x0013 – 0x0014] [0x0000]
INTLEVEL configures the Interrupt Assert Wait Time (I_AWT). When the next interrupt
occurs, Interrupt PIN (INTn ) will assert to low after INTLEVEL time.
𝐼_{𝐴𝑊𝑇} = (𝐼𝑁𝑇𝐿𝐸𝑉𝐸𝐿 + 1) × 𝑃𝐿𝐿_{𝐶𝐿𝐾} × 4 (when INTLEVEL > 0)
PLL_CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SIR 0x0000 0x0001
0x0003
0x0002
S0_IR 0x00
0x04
0x00
b.
S1_IR 0x00
0x01
a.
INTn
c.
I_AWT
d.
Figure 21. INTLEVEL Timing
a. When Timeout Interrupt of Socket 0 is occurred, S0_IR[3] & SIR[0] bit set as „1‟
and then INTn PIN is asserted to low.
b. When the connection interrupt of Socket 1 is occurred before the previous
interrupt processing is not completed, S1_IR[0] & SIR[1] bits set as „1‟ and INTn PIN is
still low.
c. If the host processed the previous interrupt completely by clearing the S0_IR[3]
bit, INTn PIN is de-asserted to high but S1_IR[0] & SIR[1] is still set as „1‟.
d. Although S1_IR[0] & SIR[1] bit is set as „1‟, the INTn can‟t be asserted to low
during INTLEVEL time. After the INTLEVEL time expires, the INTn will be asserted to
low.
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W5500 Datasheet Version1.0 (August 2013)