W5500 Datasheet, PDF (30/65 Pages) List of Unclassifed Manufacturers – Supports 8 independent sockets simultaneously

3.2 Socket Register Block
W5500 supports 8 Sockets for communication channel. Each Socket is controlled by Socket n
Register Block(when 0≤n≤7). The n value of Socket n Register can be selected by BSB[4:0] of
SPI Frame. <Table 4> defines the 16bits Offset Address of registers in Socket n Register Block.
Refer to „Chapter 4.2‟ for more details about each register.
Table 4. Offset Address in Socket n Register Block (0≤n≤7)
Offset
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
0x000A
0x000B
0x000C
0x000D
0x000E
0x000F
Register
Offset
Register
Offset
Register
Socket n Mode
Socket n Destination Port
Socket n TX Write
(Sn_MR)
0x0010 (Sn_DPORT0)
0x0024 Pointer
Socket n Command (Sn_CR) 0x0011 (Sn_DPORT1)
0x0025 (Sn_TX_WR0)
(Sn_TX_WR1)
Socket n
Socket n RX Received
Socket n Interrupt
Maximum Segment Size 0x0026 Size
(Sn_IR)
0x0012 (Sn_MSSR0)
0x0027 (Sn_RX_RSR0)
0x0013 (Sn_MSSR1)
(Sn_RX_RSR1)
Socket n Status
Socket n RX Read
(Sn_SR)
0x0014 Reserved
0x0028 Pointer
Socket n Source Port
(Sn_PORT0)
(Sn_PORT1)
0x0015
Socket n IP TOS
(Sn_TOS)
0x0029 (Sn_RX_RD0)
(Sn_RX_RD1)
Socket n RX Write
Socket n IP TTL
0x002A Pointer
Socket n Destination 0x0016 (Sn_TTL)
0x002B (Sn_RX_WR0)
Hardware Address
(Sn_RX_WR1)
(Sn_DHAR0)
0x0017
Socket n Interrupt Mask
(Sn_DHAR1)
~
Reserved
0x002C (Sn_IMR)
(Sn_DHAR2)
0x001D
Socket n Fragment
(Sn_DHAR3)
Socket n Receive Buffer
Offset in IP header
(Sn_DHAR4)
0x001E Size
0x002D (Sn_FRAG0)
(Sn_DHAR5)
(Sn_RXBUF_SIZE)
0x002E (Sn_FRAG1)
Socket n
0x001F Transmit Buffer Size
Keep alive timer
(Sn_TXBUF_SIZE)
0x002F (Sn_KPALVTR)
Socket n
Socket n TX Free Size
Destination IP Address
0x0020 (Sn_TX_FSR0)
0x0030 Reserved
(Sn_DIPR0)
0x0021 (Sn_TX_FSR1)
~
(Sn_DIPR1)
(Sn_DIPR2)
(Sn_DIPR3)
0x0022
0x0023
Socket n TX Read Pointer 0xFFFF
(Sn_TX_RD0)
(Sn_TX_RD1)
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W5500 Datasheet Version1.0 (August 2013)