W5500 Datasheet, PDF (21/65 Pages) List of Unclassifed Manufacturers – Supports 8 independent sockets simultaneously

2.3.2 Read Access in VDM
SPI Frame Start
SCSn
SCSn shoud be remained low until SPI Frame Transmit & Receive done.
MODE3
SCLK MODE0
MOSI
012
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
16bits Offset Address
BSB[4:0]
RWB OM[1:0]
15 14 13
3 2 1 0 4 3 2 1 0_{R 0 0}
8-bit Data 1
MISO
SCSn
SCLK
MOSI
7 6 5 4321 0
SCSn Should be remained low until SPI Frame Transmit & Receive done.
SPI Frame End
32 33 34 35 36 37 38 39
...
8N + 16
8N + 24
8-bit Data 2
...
8-bit Data N
MISO
7 6 5 4321 0 7 6 5 4321 07 6 5 432 10
Figure 11. Read SPI Frame in VDM mode
Figure 11 shows the SPI Frame when external host accesses W5500 for reading
In VDM mode, the RWB signal is „0‟ (Write), OM[1:0] is „00‟ in SPI Frame Control
Phase.
At this time the External Host assert (High-to-Low) SCSn signal before transmitting
SPI Frame.
Then the Host transmits Address and Control Phase all bits to W5500 through MOSI
signal. All bits are synchronized with the falling edge of the SCLK.
Then the Host receives all bits of Data Phase with synchronizing the rising edge of
Sampling SCLK through MISO signal.
After finishing the Data Phase receive, the Host deasserts SCSn signal (Low-to-
High).
When SCSn is Low and the Data Phase continues to receive, the Sequential Data
Read can be supported.
W5500 Datasheet Version1.0 (August 2013)
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