W5500 Datasheet, PDF (16/65 Pages) List of Unclassifed Manufacturers – Supports 8 independent sockets simultaneously

10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Selects Socket 5 TX Buffer
Selects Socket 5 RX Buffer
Reserved
Selects Socket 6 Register
Selects Socket 6 TX Buffer
Selects Socket 6 RX Buffer
Reserved
Selects Socket 7 Register
Selects Socket 7 TX Buffer
Selects Socket 7 RX Buffer
If the Reserved Bits are selected, it can cause the mal-function of the
W5500.
Read/Write Access Mode Bit
This sets Read/Write Access Mode.
2
RWB
„0‟ : Read
„1‟ : Write
SPI Operation Mode Bits
This sets the SPI Operation Mode.
SPI Operation Mode supports two modes, the Variable Length Data
Mode and the Fixed Length Data Mode.
1~0 OM [1:0]
- Variable Length Data Mode (VDM)
: Data Length is controlled by SCSn.
External Host makes SCSn Signal Assert (High-to-Low) and informs
the start of the SPI Frame Address Phase to W5500.
Then the external host transfers the Control Phase with
OM[1:0]=‟00‟.
After N-Bytes Data Phase transfers, SCSn Signal is De-asserted
(Low-to-High) and informs the end of the SPI Frame Data Phase to
W5500.
In VDM Mode, the SCSn must be controlled with SPI Frame unit by
the External Host. (Refer to the Figure 4)
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W5500 Datasheet Version1.0 (August 2013)