SMC91C100 Datasheet, PDF (9/83 Pages) List of Unclassifed Manufacturers – FEAST Fast Ethernet Controller

PIN NO.
1
195
6
194
30
19
12
18
25,26,
28,29
9
17
DESCRIPTION OF PIN FUNCTIONS
NAME
BUFFER
SYMBOL
TYPE
DESCRIPTION
nLink Status nLNK
IP
Input. General purpose input port used to
convey LINK status (EPHSR bit 14).
Independent of port selection (MIISEL=X).
nFullstep nFSTEP
O4
Output. Non volatile output pin. Driven by
inverse of FULLSTEP (CONFIG bit 10).
Independent of port selection (MII SEL=X).
MII Select MIISEL
O4
Output. Non volatile output pin. Driven by MII
SELECT (CONFIG bit 15). High indicates the
MII port is selected, low indicates the 10 Mbps
ENDEC is selected.
AUI Select AUISEL
O4
Output. Non volatile output pin. Driven by AUI
SELECT (CONFIG bit 8). Independent of port
selection (MIISEL=X).
Transmit
Enable 100
Mbps
TXEN100
O4
Output to MII PHY. Envelope to 100 Mbps
transmission. This pin stays low if MIISEL is
low.
Carrier 100 CRS100
Mbps
IP
Input from MII PHY. Envelope of packet
reception used for deferral and backoff
purposes. This pin is ignored when MIISEL is
low.
Receive
RX_DV
Data Valid
ID
Input from MII PHY. Envelope of data valid
reception. Used for receive data framing. This
pin is ignored when MIISEL is low.
Collision
Detect 100
Mbps
COL100
ID
Input from MII PHY. Collision detection input.
This pin is ignored when MIISEL is low.
Transmit
TXD0-TXD3
O4
Outputs. Transmit Data nibble to MII PHY.
Data
Transmit
Clock
TX25
IP
Input. Transmit clock input from MII. Nibble
rate clock (25 MHz). This pin is ignored when
MIISEL is low.
Receive
Clock
RX25
IP
Input. Receive clock input from MII PHY.
Nibble rate clock. This pin is ignored when
MIISEL is low.
9