SMC91C100 Datasheet, PDF (36/83 Pages) List of Unclassifed Manufacturers – FEAST Fast Ethernet Controller

101 5)
RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet specified in the
PACKET NUMBER REGISTER. Should not be used for frames pending transmission. Typically
used to remove transmitted frames, after reading their completion status. Can be used following
3) to release receive packet memory in a more flexible way than 4).
110 6) ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a
packet just loaded into RAM. The packet number to be enqueued is taken from the PACKET
NUMBER REGISTER.
111 7)
RESET TX FIFOs - This command will reset both TX FIFOs--theTX FIFO holding the
packet numbers awaiting transmission and the TX Completion FIFO. This command
provides a mechanism for canceling packet transmissions, and reordering or bypassing
the transmit queue. The RESET TX FIFOs command should only be used when the
transmitter is disabled. Unlike the RESET MMU command, the RESET TX FIFOs does
not release any memory.
Note 1: Bits N2,N1,N0 bits are ignored by the SMC91C100 but should be used for Command 0) to
preserve software compatibility with the SMC91C92 and future devices. They should be zero for
all other commands.
Note 2: When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory
associated with outstanding packets, or re-enqueuing them. Packet numbers in the completion
FIFO can be read via the FIFO ports register before issuing the command.
Note 3: MMU commands releasing memory (commands 4 and 5) should only be issued if the
corresponding packet number has memory allocated to it.
COMMAND SEQUENCING
A second allocate command (command 1) should
not be issued until the present one has
completed. Completion is determined by reading
the FAILED bit of the allocation result register or
through the allocation interrupt.
A second release command (commands 4, 5)
should not be issued if the previous one is still
being processed. The BUSY bit indicates that a
release command is in progress. After issuing
command 5, the contents of the PNR should not
be changed until BUSY goes low. After issuing
command 4, command 3 should not be issued
until BUSY goes low.
BUSY BIT Readable at bit 0 of the MMU
command register address. When set indicates
that MMU is still processing a release command.
When clear, MMU has already completed last
release command. BUSY and FAILED bits are
set upon the trailing edge of command.
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