SMC91C100 Datasheet, PDF (14/83 Pages) List of Unclassifed Manufacturers – FEAST Fast Ethernet Controller

FUNCTIONAL DESCRIPTION
DESCRIPTION OF BLOCKS
Clock Generator Block
The SMC91C100's clock generator uses a 25 MHz
crystal connected to pins XTAL1 XTAL2 and
generates two free running clocks:
1) 50 MHz free running clock - Supplied to the
DMA and the ARBITER blocks.
2) 25 MHz free running clock - Used to run the
EPH during reset or when no TX25 is present.
the DMA block. The DMA port of the FIFO stores
32 bits exploiting the 32-bit data path into memory.
The Control Path consists of a set of registers
interfaced to the CPU via the BIU.
DMA Block
This block accesses packet memory on the
CSMA/CD's behalf, fetching transmit data and
storing received data. It interfaces the CSMA/CD
Transmit and Receive FIFOs on one side, and the
Arbiter block on the other. The data path is 32 bits
wide.
Other clocks:
3) TXCLK and RXCLK are 10 MHz clock inputs.
These clocks are generated by the external
ENDEC in 10 Mbps mode and are only used
by the CSMA/CD block.
4) TX25 is an input clock. It will be the nibble rate
of the particular PHY connected to the MII (2.5
MHz for a 10 Mbps PHY, and 25 MHz for a
100 Mbps PHY).
5) RX25 - This is the MII nibble rate receive clock
used for sampling received data nibbles and
running the receive state machine (2.5 MHz for
a 10 Mbps PHY, and 25 MHz for a 100 Mbps
PHY).
The DMA machine is able to support full duplex
operation. Independent receive and transmit
counters are used. Transmit and receive cycles are
alternated when simultaneous receive and transmit
accesses are needed.
Arbiter Block
The Arbiter block sequences accesses to packet
RAM requested by the BIU and by the DMA blocks.
BIU requests represent pipelined CPU accesses to
the Data Register, while DMA requests represent
CSMA/CD data movement. The external memory
devices used are 25ns 32kx8 SRAM. The cycle
time for CPU consecutive accesses to the Data
Path is 80ns/doubleword. This time includes
arbitration and CSMA memory cycles.
6) LCLK - Bus clock - Used by the BIU for
synchronous accesses. Maximum frequency is
50 MHz for VL BUS mode, and 8.5 MHz for
EISA slave DMA.
CSMA/CD Block
The Arbiter is also responsible for controlling the
nRWE0-nRWE3 lines as a function of the bytes
being written. Read accesses are always 32 bits
wide, and the Arbiter steers the appropriate byte(s)
to the appropriate lanes as a function of the
address.
This is a 16-bit oriented block, with fully-
independent Transmit and Receive logic. The data
path in and out of the block consists of two 16-bit
wide uni-directional FIFOs interfacing
The CPU Data Path consists of two uni-directional
FIFOs mapped at the Data Register location. These
FIFOs can be accessed in any
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