SMC91C100 Datasheet, PDF (62/83 Pages) List of Unclassifed Manufacturers – FEAST Fast Ethernet Controller

APPLICATION CONSIDERATIONS
The SMC91C100 is envisioned to fit a few different
bus types. This section describes the basic
guidelines, system level implications and sample
configurations for the most relevant bus types. All
applications are based on buffered architectures
with a private SRAM bus.
FAST ETHERNET SLAVE ADAPTER
e) 100 Mbps MII compliant PHY
f) Some bus specific glue logic
Target systems:
a) VL Local Bus 32 bit systems
b) High-end ISA machines
c) EISA 32 bit slave
Slave non-intelligent board implementing 100 Mbps
and 10 Mbps speeds.
Adapter requires:
a) SMC91C100 Fast Ethernet Controller
b) Four SRAMs (32k x 8 - 25ns)
c) Serial EEPROM (93C46)
d) 10 Mbps ENDEC and transceiver chip
VL Local Bus 32 Bit Systems
On VL Local Bus and other 32 bit embedded
systems, the SMC91C100 is accessed as a 32 bit
peripheral in terms of the bus interface. All registers
except the DATA REGISTER will be accessed
using byte or word instructions. Accesses to the
DATA REGISTER could use byte, word, or dword
instructions.
VL
BUS
SIGNA
L
A2-A15
M/nIO
W /nR
nRDYR
TN
nLRDY
LCLK
nRESE
T
SMC91C10
0 SIGNAL
A2-A15
AEN
W /nR
nRDYRTN
nSRDY
and some
logic
LCLK
RESET
Table 3 - VL Local Bus Signal Connections
NOTES
Address bus used for I/O space and register decoding, latched by nADS rising
edge, and transparent on nADS low time
Qualifies valid I/O decoding - enabled access when low. This signal is latched by
nADS rising edge and transparent on nADS low time
Direction of access. Sampled by the SMC91C100 on first rising clock that has
nCYCLE active. High on writes, low on reads.
Ready return. Direct connection to VL bus.
nSRDY has the appropriate functionality and timing to create the VL nLRDY
except that nLRDY behaves like an open drain output most of the time.
Local Bus Clock. Rising edges used for synchronous bus interface transactions.
Connected via inverter to the SMC91C100.
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