SMC91C100 Datasheet, PDF (57/83 Pages) List of Unclassifed Manufacturers – FEAST Fast Ethernet Controller

SMC91C100 is virtually queuing the packet
numbers and their status words.
In this case, the transmit interrupt service routine
can find the next packet number to be serviced by
reading the TX DONE PACKET NUMBER at the
FIFO PORTS register. This eliminates the need for
the driver to keep a list of packet numbers being
transmitted. The numbers are queued by the
SMC91C100 and provided back to the CPU as their
transmission completes.
2) One interrupt per sequence of packets: Enable
TX EMPTY INT and TX INT, set AUTO
RELEASE=1. TX EMPTY INT is generated only
after transmitting the last packet in the FIFO.
TX INT will be set on a fatal transmit error allowing
the CPU to know that the transmit
process has stopped and therefore the FIFO will not
be emptied.
This mode has the advantage of a smaller CPU
overhead, and faster memory de-allocation. Note
that when AUTO RELEASE=1 the CPU is not
provided with the packet numbers that completed
successfully.
Note: The pointer register is shared by any process
accessing the SMC91C100 memory. In order to
allow processes to be interruptable, the interrupting
process is responsible for reading the pointer value
before modifying it, saving it, and restoring it before
returning from the interrupt.
Typically there would be three processes using the
pointer:
1) Transmit loading (sometimes interrupt driven)
2) Receive unloading (interrupt driven)
3) Transmit Status reading (interrupt driven).
1) and 3) also share the usage of the Packet
Number Register. Therefore saving and restoring
the PNR is also required from interrupt service
routines.
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