SMC91C100 Datasheet, PDF (66/83 Pages) List of Unclassifed Manufacturers – FEAST Fast Ethernet Controller

EISA 32 BIT SLAVE
On EISA, the SMC91C100 is accessed as a 32 bit
I/O slave, along with a Slave DMA type "C" data
path option. As an I/O slave, the SMC91C100 uses
asynchronous accesses. In creating nRD and nWR
inputs, the timing information is externally derived
from nCMD edges. Given that the access will be at
least 1.5 to 2 clocks (more than 180ns at least)
there is no need to negate EXRDY, simplifying the
EISA interface implementation. As a DMA Slave,
the
SMC91C100 accepts burst transfers, and is able to
sustain the peak rate of one doubleword every
BCLK. Doubleword alignment is assumed for DMA
transfers. Up to 3 extra bytes in the beginning and at
the end of the transfer should be moved by the CPU
using I/O accesses to the Data Register. The
SMC91C100 will sample EXRDY and postpone
DMA cycles if the memory cycle solicits wait states.
EISA BUS
SIGNAL
LA2-15
M/nIO
AEN
Latched W-R
combined with
nCMD
Latched W-R
combined with
nCMD
nSTART
RESDRV
nBE0, nBE1,
nBE2, nBE3
IRQn
Table 5 - EISA 32 Bit Slave Signal Connections
SMC91C100 SIGNAL
NOTES
A2-A15
Address bus used for I/O space and register decoding,
latched by nADS (nSTART) trailing edge.
AEN
Qualifies valid I/O decoding - enabled access when low.
These signals are externally ORed. Internally the AEN pin is
latched by nADS rising edge and transparent while nADS is
low.
nRD
I/O Read strobe - Asynchronous read accesses. Address is
valid before its leading edge. Must not be active during DMA
bursts if DMA is supported.
nW R
I/O Write strobe - Asynchronous write access. Address is
valid before leading edge. Data latched on trailing edge.
Must not be active during DMA bursts if DMA is supported.
nADS
Address strobe is connected to EISA nSTART.
RESET
nBE0, nBE1,
nBE2, nBE3
Byte enables. Latched on nADS rising edge.
INTR0-INTR3
Interrupts used as active high edge triggered.
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