SMC91C100 Datasheet, PDF (23/83 Pages) List of Unclassifed Manufacturers – FEAST Fast Ethernet Controller

I/O SPACE - BANK 0
OFFSET
NAME
TYPE
SYMBOL
2
EPH STATUS REGISTER
READ ONLY
EPHSR
This register stores the status of the last frame transmitted. This register value, upon individual transmit
packet completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt
processing should use the copy in memory as the register itself will be updated by subsequent packet
transmissions. The register can be used for real time values (like TXENA and LINK OK). If TXENA is
cleared the register holds the last packet completion status.
HIGH
BYTE
TX UNRN
LINK_OK
RX_OVR
N
CTR_ROL EXC_DEF
LOST
CARR
LATCOL
0
-nLNK Pin
0
0
0
0
0
X
LOW
BYTE
TX DEFR LTX BRD
0
0
SQET
0
16COL
0
LTX
MULT
0
MUL COL
0
SNGL
COL
0
TX_SUC
0
TXUNRN Transmit Under Run. Set if under run
occurs, it also clears TXENA bit in TCR. Cleared
by setting TXENA high. This bit should never be
set under normal operation.
LINK_OK General purpose input port driven by
nLNK pin inverted. Typically used for LINK Test.
A transition on the value of this bit generates an
interrupt.
RX_OVRN Upon FIFO overrun, the receiver
asserts this bit and clears the FIFO. The receiver
stays enabled. After a valid preamble has been
detected on a subsequent frame, RX_OVRN is
de-asserted. The RX_OVRN INT bit in the
Interrupt Status Register will also be set and stay
set until cleared by the CPU. Note that receive
overruns could occur only if receive memory
allocations fail.
CTR_ROL Counter Roll Over. When set, one or
more 4-bit counters have reached maximum
count (15). Cleared by reading the ECR register.
EXC_DEF Excessive Deferral. When set
last/current transmit was deferred for more than
1518 * 2 byte times. Cleared at the end of every
packet sent.
LOST_CARR Lost Carrier Sense. When set,
indicates that Carrier Sense was not present at
end of preamble. Valid only if MON_CSN is
enabled. This condition causes TXENA bit in
TCR to be reset. Cleared by setting TXENA bit in
TCR.
LATCOL Late collision detected on last transmit
frame. If set, a late collision was detected (later
than 64 byte times into the frame). When
detected, the transmitter JAMs and turns itself off,
clearing the TXENA bit in TCR. Cleared by
setting TXENA in TCR.
TX_DEFR Transmit Deferred. When set, carrier
was detected during the first 6.4 µsec of the inter
frame gap. Cleared at the end of every packet
sent.
LTX_BRD Last transmit frame was a broadcast.
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