SMC91C100 Datasheet, PDF (50/83 Pages) List of Unclassifed Manufacturers – FEAST Fast Ethernet Controller

TYPICAL FLOW OF EVENTS FOR RECEIVE
S/W DRIVER
MAC SIDE
1 ENABLE RECEPTION - By setting the RXEN bit.
2
A packet is received with matching address.
Memory is requested from MMU. A packet
number is assigned to it. Additional memory is
requested if more pages are needed.
3
The internal DMA logic generates sequential
addresses and writes the receive words into
memory. The MMU does the sequential to
physical address translation. If overrun, packet is
dropped and memory is released.
4
W hen the end of packet is detected, the status
word is placed at the beginning of the receive
packet in memory. Byte count is placed at the
second word. If the CRC checks correctly the
packet number is written into the RX FIFO. The
RX FIFO being not empty causes RCV INT
(interrupt) to be set. If CRC is incorrect the packet
memory is released and no interrupt will occur.
5 SERVICE INTERRUPT - Read the Interrupt
Status Register and determine if RCV INT is set.
The next receive packet is at receive area. (Its
packet number can be read from the FIFO Ports
Register). The software driver can process the
packet by accessing the RX area, and can move
it out to system memory if desired. When
processing is complete the CPU issues the
REMOVE AND RELEASE FROM TOP OF RX
command to have the MMU free up the used
memory and packet number.
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