SMC91C100 Datasheet, PDF (28/83 Pages) List of Unclassifed Manufacturers – FEAST Fast Ethernet Controller

I/O SPACE - BANK 0
OFFSET
A
NAME
MEMORY CONFIGURATION REGISTER
TYPE
Lower Byte -
READ/WRITE
Upper Byte -
READ ONLY
SYMBOL
MCR
HIGH
BYTE
MEMORY SIZE MULTIPLIER
(M)
0
0
1
1
0
1
0
1
LOW
BYTE
MEMORY RESERVED FOR TRANSMIT (IN BYTES * 256 * M)
0
0
0
0
0
0
0
0
MEMORY RESERVED FOR TRANSMIT
Programming this value allows the host CPU to
reserve memory to be used later for transmit,
limiting the amount of memory that receive
packets can use up. When programmed for zero,
the memory allocation between transmit and
receive is completely dynamic. When
programmed for a non-zero value, the allocation is
dynamic if the free memory exceeds the
programmed value, while receive allocation
requests are denied if the free memory is less or
equal to the programmed value. This register
defaults to zero upon reset. It is not affected by
the RESET MMU command.
The value written to the MCR is a reserved
memory space IN ADDITION TO ANY MEMORY
CURRENTLY IN USE. If the memory allocated for
transmit plus the reserved space for transmit is
required to be constant (rather than grow with
transmit allocations), the CPU should update the
value of this register after allocating or releasing
memory.
The contents of MIR as well as the low byte of
MCR are specified in 256 * M bytes. The
multiplier M is determined by bits 11, 10, and 9 as
follows (Bits 11, 10 and 9 are read only bits used
by the software driver to transparently run on
different controllers of the SMC9000 family):
DEVICE
bit 11 bit10 bit 9
M
SMC91C100 0
1
0
2
SMC91C90
0
0
1
1
FUTURE
0
1
1
4
FUTURE
1
0
0
8
FUTURE
1
0
1
16
MAX MEMORY SIZE
256*256*2=128k
256*256*1=64k
256k
512k
1M
28