SMC91C100 Datasheet, PDF (41/83 Pages) List of Unclassifed Manufacturers – FEAST Fast Ethernet Controller

I/O SPACE - BANK2
OFFSET
NAME
C
INTERRUPT STATUS REGISTER
ERCV INT
EPH INT
RX_OVRN
INT
ALLOC
INT
X
0
0
0
0
TYPE
READ ONLY
SYMBOL
IST
TX
EMPTY
INT
1
TX INT RCV INT
0
0
OFFSET
C
NAME
TYPE
INTERRUPT ACKNOWLEDGE REGISTER WRITE ONLY
SYMBOL
ACK
ERCV INT
RX_OVRN
INT
TX
EMPTY
INT
TX INT
OFFSET
D
NAME
INTERRUPT MASK REGISTER
TYPE
READ/WRITE
SYMBOL
MSK
ERCV INT
EPH INT
RX_OVRN
INT
ALLOC
INT
TX
EMPTY
INT
TX INT RCV INT
X
0
0
0
0
0
0
0
This register can be read and written as a word or
as two individual bytes.
The Interrupt Mask Register bits enable the
appropriate bits when high and disable them when
low. An enabled bit being set will cause a
hardware interrupt.
ERCV INT Early receive interrupt. Set whenever
a receive packet is being received, and the
number of bytes received into memory exceeds
the value programmed as ERCV THRESHOLD
(Bank 3, Offset Ch). ERCV INT
stays set until acknowledged by writing the
INTERRUPT ACKNOWLEDGE REGISTER with
the ERCV INT bit set.
EPH INT Set when the Ethernet Protocol Handler
section indicates one out of various possible
special conditions. This bit merges exception type
of interrupt sources, whose service time is not
critical to the execution speed of the low level
drivers. The exact nature of the interrupt can be
obtained from the EPH Status Register (EPHSR),
and enabling of these sources can be done via
the Control Register.
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