SMC91C100 Datasheet, PDF (4/83 Pages) List of Unclassifed Manufacturers – FEAST Fast Ethernet Controller

PIN NO.
148-159
NAME
Address
145-147 Address
193
160-163
Address
Enable
nByte
Enable
173-170,
168-166,
164,144,
142-139,
137-135,
133,
131-129,
127,126,
124,123,
121,118,
117,
115-112,
110
182
Data Bus
Reset
95
nAddress
Strobe
183
nCycle
DESCRIPTION OF PIN FUNCTIONS
BUFFER
SYMBOL
TYPE
DESCRIPTION
A4-A15
I
Input. Decoded by the SMC91C100 to
determine accesses to its registers.
A1-A3
I
Input. Used by the SMC91C100 for internal
register selection.
AEN
I
Input. Used as an address qualifier. Address
decoding is only enabled when AEN is low.
nBE0-nBE3
I
Input. Used during SMC91C100 register
accesses to determine the width of the access
and the register(s) being accessed. nBE0-
nBE3 are ignored when nDATACS is low
(burst accesses) because 32 bit transfers are
assumed.
D0-D31
I/O24
Bidirectional. 32 bit data bus used to access
the SMC91C100's internal registers. Data bus
has weak internal pullups. Supports direct
connection to the system bus without external
buffering. For 16 bit systems, only D0-D15 are
used.
RESET
nADS
nCYCLE
IS
Input. This input is not considered active
unless it is active for at least 100ns to filter
narrow glitches.
IS
Input. Address strobe. For systems that require
address latching, the rising edge of nADS
indicates the latching moment for A1-A15 and
AEN. All SMC91C100 internal functions of A1-
A15, AEN are latched except for nLDEV
decoding.
I
Input. This active low signal is used to control
SMC91C100 synchronous bus cycles.
4