SMC91C100 Datasheet, PDF (20/83 Pages) List of Unclassifed Manufacturers – FEAST Fast Ethernet Controller

I/O SPACE
The base I/O space is determined by the IOS0-2
inputs and the EEPROM contents. To limit the I/O
space requirements to 16 locations, the registers are
assigned to different banks. The
OFFSET
NAME
last word of the I/O area is shared by all banks and
can be used to change the bank in use. Registers
are described using the following convention:
TYPE
SYMBOL
HIGH
BYTE
LOW
BYTE
bit 15
X
bit 7
X
bit14
X
bit 6
X
bit 13
X
bit 5
X
bit 12
X
bit 4
X
OFFSET Defines the address offset within the
IOBASE where the register can be accessed at,
provided the bank select has the appropriate value.
The offset specifies the address of the even byte
(bits 0-7) or the address of the complete word.
The odd byte can be accessed using address
(offset + 1).
bit 11
bit 10
bit9
bit8
X
X
X
X
bit 3
bit 2
bit 1 bit 0
X
X
X
X
Some registers (like the Interrupt Ack., or like
Interrupt Mask) are functionally described as two
eight bit registers, in that case the offset of each one
is independently specified.
Regardless of the functional description, all registers
can be accessed as doublewords, words or bytes.
The default bit values upon hard reset are
highlighted below each register.
Table 2 - Internal I/O Space Mapping
BANK0
BANK1
BANK2
BANK3
0
TCR
CONFIG
MMU COMMAND
MT0-1
2
EPH STATUS
BASE
PNR/ARR
MT2-3
4
RCR
IA0-1
FIFO PORTS
MT4-5
6
COUNTER
IA2-3
POINTER
MT6-7
8
MIR
IA4-5
DATA
MGMT
A
MCR
GENERAL PURPOSE
DATA
REVISION
C RESERVED (0)
CONTROL
INTERRUPT
ERCV
E BANK SELECT
BANK SELECT
BANK SELECT BANK SELECT
A special BANK (BANK7) exists to support the addition of external registers.
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