MC80F0204 Datasheet, PDF (96/126 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0104/0204
Preliminary
Oscillator
(XI pin)
STOP Mode
Internal
Clock
RESET
Internal
RESET
STOP Instruction Execution
Time can not be control by software
Stabilization Time
t_ST = 65.5mS @4MHz
Figure 19-6 Timing of STOP Mode Release by Reset
19.3 Stop Mode at Internal RC-Oscillated Watchdog Timer Mode
In the Internal RC-Oscillated Watchdog Timer mode, the
on-chip oscillator is stopped. But internal RC oscillation
circuit is oscillated in this mode. The on-chip RAM and
Control registers are held. The port pins out the values held
by their respective port data register, port direction regis-
ters.
The Internal RC-Oscillated Watchdog Timer mode is acti-
vated by execution of STOP instruction after setting the bit
RCWDT of CKCTLR to "1". (This register should be writ-
ten by byte operation. If this register is set by bit manipu-
lation instruction, for example "set1" or "clr1" instruction,
it may be undesired operation)
fines all the Control registers but does not change the on-
chip RAM. External interrupts allow both on-chip RAM
and Control registers to retain their values.
If I-flag = 1, the normal interrupt response takes place. In
this case, if the bit WDTON of CKCTLR is set to "0" and
the bit WDTE of IENH is set to "1", the device will execute
the watchdog timer interrupt service routine(Figure 8-6 ).
However, if the bit WDTON of CKCTLR is set to "1", the
device will generate the internal Reset signal and execute
the reset processing(Figure 19-8 ). If I-flag = 0, the chip
will resume execution starting with the instruction follow-
ing the STOP instruction. It will not vector to interrupt ser-
vice routine.(refer to Figure 19-4 )
Note: Caution: After STOP instruction, at least two or more NOP
instruction should be written
Ex)
LDM WDTR,#1111_1111B
LDM CKCTLR,#0010_1110B
LDM SSCR,#0101_1010B
STOP
NOP ;for stabilization time
NOP ;for stabilization time
The exit from Internal RC-Oscillated Watchdog Timer
mode is hardware reset or external interrupt or watchdog
timer interrupt (at RC-watchdog timer mode). Reset re-de-
When exit from Stop mode at Internal RC-Oscillated
Watchdog Timer mode by external interrupt, the oscilla-
tion stabilization time is required to normal operation. Fig-
ure 19-7 shows the timing diagram. When release the
Internal RC-Oscillated Watchdog Timer mode, the basic
interval timer is activated on wake-up. It is increased from
00_H until FF_H. The count overflow is set to start normal op-
eration. Therefore, before STOP instruction, user must be
set its relevant prescaler divide ratio to have long enough
time (more than 20msec). This guarantees that oscillator
has started and stabilized. By reset, exit from internal RC-
Oscillated Watchdog Timer mode is shown in Figure 19-8
.
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Mar. 2005 Ver 0.2