MC80F0204 Datasheet, PDF (46/126 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0104/0204
Preliminary
Watchdog Timer Control
Figure 12-2 shows the watchdog timer control register.
The watchdog timer is automatically disabled after reset.
The CPU malfunction is detected during setting of the de-
tection time, selecting of output, and clearing of the binary
counter. Clearing the binary counter is repeated within the
detection time.
If the malfunction occurs for any cause, the watchdog tim-
er output will become active at the rising overflow from
the binary counters unless the binary counter is cleared. At
this time, when WDTON=1, a reset is generated, which
drives the RESET pin to low to reset the internal hardware.
When WDTON=0, a watchdog timer interrupt (WDTIF) is
generated. The WDTON bit is in register CLKCTLR.
The watchdog timer temporarily stops counting in the
STOP mode, and when the STOP mode is released, it au-
tomatically restarts (continues counting).
WDTR
W
7
WDTCL
W W WW W
6
5
4
3
2
WW
1
0
ADDRESS: 0F4_H
INITIAL VALUE: 0111 1111_B
7-bit compare data
Clear count flag
0: Free-run count
1: When the WDTCL is set to “1”, binary counter
is cleared to “0”. And the WDTCL becomes “0” automatically
after one machine cycle. Counter count up again.
Figure 12-2 WDTR: Watchdog Timer Control Register
Example: Sets the watchdog timer detection time to 1 sec.
at 4.194304MHz
LDM
LDM
LDM
:
Within WDT
:
detection time ^:
:
LDM
:
Within WDT
:
detection time
:
:
LDM
CKCTLR,#3FH
WDTR,#08FH
WDTR,#08FH
WDTR,#08FH
WDTR,#08FH
;Select 1/1024 clock source, WDTON ← 1, Clear Counter
;Clear counter
;Clear counter
;Clear counter
Enable and Disable Watchdog
Watchdog timer is enabled by setting WDTON (bit 4 in
CKCTLR) to “1”. WDTON is initialized to “0” during re-
set and it should be set to “1” to operate after reset is re-
leased.
Example: Enables watchdog timer for Reset
:
LDM CKCTLR,#xxx1_xxxxB;WDTON ← 1
:
:
The watchdog timer is disabled by clearing bit 4 (WD-
TON) of CKCTLR. The watchdog timer is halted in STOP
mode and restarts automatically after STOP mode is re-
leased.
Watchdog Timer Interrupt
The watchdog timer can be also used as a simple 7-bit tim-
er by clearing bit4 of CKCTLR to “0”. The interval of
watchdog timer interrupt is decided by Basic Interval Tim-
er. Interval equation is shown as below.
T_WDT = (WDTR+1) × Interval of BIT
The stack pointer (SP) should be initialized before using
the watchdog timer output as an interrupt source.
Example: 7-bit timer interrupt set up.
LDM CKCTLR,#xxx0_xxxxB;WDTON ←0
LDM WDTR,#8FH ;WDTCL ←1
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Mar. 2005 Ver 0.2