MC80F0204 Datasheet, PDF (45/126 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

Preliminary
MC80F0104/0204
12. WATCHDOG TIMER
The watchdog timer rapidly detects the CPU malfunction
such as endless looping caused by noise or the like, and re-
sumes the CPU to the normal state. The watchdog timer
signal for detecting malfunction can be selected either a re-
set CPU or a interrupt request.
When the watchdog timer is not being used for malfunc-
tion detection, it can be used as a timer to generate an in-
terrupt at fixed intervals.
The watchdog timer has two types of clock source. The
first type is an on-chip RC oscillator which does not re-
quire any external components. This RC oscillator is sepa-
rate from the external oscillator of the X_IN pin. It means
that the watchdog timer will run, even if the clock on the
X_IN pin of the device has been stopped, for example, by en-
tering the STOP mode. The other type is a prescaled sys-
tem clock.
The watchdog timer consists of 7-bit binary counter and
the watchdog timer data register. When the value of 7-bit
binary counter is equal to the lower 7 bits of WDTR, the
interrupt request flag is generated. This can be used as
Watchdog timer interrupt or reset the CPU in accordance
with the bit WDTON.
Note: Because the watchdog timer counter is enabled after clear-
ing Basic Interval Timer, after the bit WDTON set to "1", maximum
error of timer is depend on prescaler ratio of Basic Interval Timer.
The 7-bit binary counter is cleared by setting WDTCL(bit7 of
WDTR) and the WDTCL is cleared automatically after 1 machine
cycle.
The RC oscillated watchdog timer is activated by setting
the bit RCWDT as shown below.
LDM
LDM
LDM
STOP
NOP
NOP
:
CKCTLR,#3FH; enable the RC-OSC WDT
WDTR,#0FFH ; set the WDT period
SSCR, #5AH ;ready for STOP mode
; enter the STOP mode
; RC-OSC WDT running
The RC-WDT oscillation period is vary with temperature,
V_DD and process variations from part to part (approxi-
mately, 33~100uS). The following equation shows the
RCWDT oscillated watchdog timer time-out.
T_RCWDT=CLK_RCWDT×2⁸×WDTR + (CLK_RCWDT×2⁸⁾/2
where, CLK_RCWDT = 33~100uS
In addition, this watchdog timer can be used as a simple 7-
bit timer by interrupt WDTIF. The interval of watchdog
timer interrupt is decided by Basic Interval Timer. Interval
equation is as below.
T_WDT = (WDTR+1) × Interval of BIT
BASIC INTERVAL TIMER
OVERFLOW
Count
source
clear
Watchdog
Counter (7-bit)
clear
WDTCL
comparator
7-bit compare data
[0F4_H]
7
WDTR
Watchdog Timer
Register
Internal bus line
“0”
“1”
enable
to reset CPU
WDTON in CKCTLR [0F2_H]
WDTIF
Watchdog Timer interrupt
Figure 12-1 Block Diagram of Watchdog Timer
Mar. 2005 Ver 0.2
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