MC80F0204 Datasheet, PDF (93/126 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

Preliminary
.
Oscillator
(X_IN pin)
Internal Clock
External Interrupt
Normal Operation
SLEEP Instruction
Executed
SLEEP Operation
MC80F0104/0204
Normal Operation
Figure 19-2 SLEEP Mode Release Timing by External Interrupt
Oscillator
(X_IN pin)
CPU
Clock
RESET
Internal
RESET
SLEEP Instruction
Execution
Normal Operation
SLEEP Operation
Stabilization Time
t_ST = 65.5mS @4MHz
Normal Operation
Figure 19-3 Timing of SLEEP Mode Release by Reset
19.2 Stop Mode
In the Stop mode, the main oscillator, system clock and pe-
ripheral clock is stopped, but RC-oscillated watchdog tim-
er continue to operate. With the clock frozen, all functions
are stopped, but the on-chip RAM and Control registers are
held. The port pins out the values held by their respective
port data register, port direction registers. Oscillator stops
and the systems internal operations are all held up.
• The states of the RAM, registers, and latches valid
immediately before the system is put in the STOP
state are all held.
• The program counter stop the address of the
instruction to be executed after the instruction
"STOP" which starts the STOP operating mode.
Note: The Stop mode is activated by execution of STOP instruc-
tion after setting the SSCR to “5A_H”. (This register should be writ-
ten by byte operation. If this register is set by bit manipulation
instruction, for example "set1" or "clr1" instruction, it may be undes-
ired operation)
In the Stop mode of operation, V_DD can be reduced to min-
imize power consumption. Care must be taken, however,
to ensure that V_DD is not reduced before the Stop mode is
invoked, and that V_DD is restored to its normal operating
level, before the Stop mode is terminated.
Mar. 2005 Ver 0.2
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