MC80F0204 Datasheet, PDF (88/126 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0104/0204
Preliminary
main task
acceptance of
interrupt
interrupt
service task
saving
registers
interrupt return
restoring
registers
18.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction,
which has the lowest priority order.
Interrupt vector address of BRK is shared with the vector
of TCALL 0 (Refer to Program Memory Section). When
BRK interrupt is generated, B-flag of PSW is set to distin-
guish BRK from TCALL 0.
Each processing step is determined by B-flag as shown in
Figure 18-5 .
BRK or
TCALL0
B-FLAG
=1
BRK
INTERRUPT
ROUTINE
=0
TCALL0
ROUTINE
RETI
RET
18.3 Multi Interrupt
If two requests of different priority levels are received si-
multaneously, the request of higher priority level is ser-
viced. If requests of the interrupt are received at the same
time simultaneously, an internal polling sequence deter-
mines by hardware which request is serviced. However,
Figure 18-5 Execution of BRK/TCALL0
multiple processing through software for special features is
possible. Generally when an interrupt is accepted, the I-
flag is cleared to disable any further interrupt. But as user
sets I-flag in interrupt routine, some further interrupt can
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