MC80F0204 Datasheet, PDF(85/126 Page) List of Unclassifed Manufacturers

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MC80F0204 Datasheet, PDF (85/126 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

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Preliminary

MC80F0104/0204

The Basic Interval Timer Interrupt is generated by BITIF

which is set by a overflow in the timer counter register.

The UART receive or transmit interrupts are generated by

UARTRIF or UARTTIF are set by completion of UART

data reception or transmission.

The SIO interrupt is generated by SIOIF which is set by

completion of SIO data reception or transmission.

The interrupts are controlled by the interrupt master enable

flag I-flag (bit 2 of PSW on Figure 8-3 ), the interrupt en-

able register (IENH, IENL), and the interrupt request flags

(in IRQH and IRQL) except Power-on reset and software

BRK interrupt. The Table 18-1 shows the Interrupt priori-

ty.

Vector addresses are shown in Figure 8-6 . Interrupt enable

registers are shown in Figure 18-2 . These registers are

composed of interrupt enable flags of each interrupt source

and these flags determines whether an interrupt will be ac-

cepted or not. When enable flag is â0â, a corresponding in-

terrupt source is prohibited. Note that PSW contains also a

master enable bit, I-flag, which disables all interrupts at

once.

Reset/Interrupt

Hardware Reset

External Interrupt 0

External Interrupt 1

External Interrupt 2

External Interrupt 3

UART Rx Interrupt

UART Tx Interrupt

Serial Input/Output

Timer/Counter 0

Timer/Counter 1

Timer/Counter 2

Timer/Counter 3

ADC Interrupt

Watchdog Timer

Basic Interval Timer

Symbol

RESET

INT0

INT1

INT2

INT3

INT_RX

INT_TX

SIO

Timer 0

Timer 1

Timer 2

Timer 3

ADC

WDT

BIT

Priority

Table 18-1 Interrupt Priority

R/W R/W R/W R/W R/W R/W R/W R/W

IENH INT0E INT1E INT2E INT3E UARTRE UARTTE SIOE T0E

MSB

LSB

ADDRESS: 0EAH

INITIAL VALUE: 0000 0000B

Timer/Counter 0 interrupt enable flag

Serial Communication interrupt enable flag

UART Tx interrupt enable flag

UART Rx interrupt enable flag

External interrupt 0 enable flag

External interrupt 1 enable flag

External interrupt 2 enable flag

External interrupt 3 enable flag

R/W

IENL T1E

MSB

R/W

T2E

R/W

T3E

R/W R/W R/W R/W

- ADCE WDTE -

R/W

BITE

LSB

ADDRESS: 0EBH

INITIAL VALUE: 000- 00-0B

Basic Interval Timer interrupt enable flag

Watchdog timer interrupt enable flag

A/D Converter interrupt enable flag

Timer/Counter 3 interrupt enable flag

Timer/Counter 2 interrupt enable flag

Timer/Counter 1 interrupt enable flag

Figure 18-2 Interrupt Enable Flag Register

Mar. 2005 Ver 0.2

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