MC80F0204 Datasheet, PDF(94/126 Page) List of Unclassifed Manufacturers

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MC80F0204 Datasheet, PDF (94/126 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

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MC80F0104/0204

Preliminary

The reset should not be activated before VDD is restored to

its normal operating level, and must be held active long

enough to allow the oscillator to restart and stabilize.

Note: After STOP instruction, at least two or more NOP instruc-

tion should be written.

Ex)

LDM CKCTLR,#0FH ;more than 20ms

LDM SSCR,#5AH

STOP

NOP ;for stabilization time

In the STOP operation, the dissipation of the power asso-

ciated with the oscillator and the internal hardware is low-

ered; however, the power dissipation associated with the

pin interface (depending on the external circuitry and pro-

gram) is not directly determined by the hardware operation

of the STOP feature. This point should be little current

flows when the input level is stable at the power voltage

level (VDD/VSS); however, when the input level gets high-

er than the power voltage level (by approximately 0.3 to

0.5V), a current begins to flow. Therefore, if cutting off the

output transistor at an I/O port puts the pin signal into the

high-impedance state, a current flow across the ports input

transistor, requiring to fix the level by pull-up or other

means.

Peripheral

CPU

RAM

Basic Interval Timer

Watchdog Timer

Timer/Counter

Buzzer, ADC

SIO

UART

Oscillator

I/O Ports

Control Registers

Internal Circuit

Prescaler

Address Data Bus

Release Source

STOP Mode

Stop

Retain

Halted

Stop (Only operates in RC-WDT mode)

Halted (Only when the event counter mode

is enabled, timer operates normally)

Stop

Only operate with external clock

Stop (XIN=L, XOUT=H)

Retain

Stop mode

Retain

Reset, Timer(EC0,1), SIO, UART(using

ACLK), Watchdog Timer (RC-WDT mode),

External Interrupt

SLEEP Mode

Stop

Retain

Operates Continuously

Stop

Operates Continuously

Stop

Only operate with external clock

Oscillation

Retain

Sleep mode

Active

Retain

Reset, All Interrupts

Table 19-1 Peripheral Operation During Power Saving Mode

Release the STOP mode

The source for exit from STOP mode is hardware reset, ex-

ternal interrupt, Timer(EC0,1), Watch Timer, WDT, SIO

or UART. Reset re-defines all the Control registers but

does not change the on-chip RAM. External interrupts al-

low both on-chip RAM and Control registers to retain their

values.

If I-flag = 1, the normal interrupt response takes place. If I-

flag = 0, the chip will resume execution starting with the

instruction following the STOP instruction. It will not vec-

tor to interrupt service routine. (refer to Figure 19-4 )

When exit from Stop mode by external interrupt, enough

oscillation stabilizing time is required to normal operation.

Figure 19-5 shows the timing diagram. When released

from the Stop mode, the Basic interval timer is activated on

wake-up. It is increased from 00H until FFH. The count

overflow is set to start normal operation. Therefore, before

STOP instruction, user must be set its relevant prescaler di-

vide ratio to have long enough time (more than 20msec).

This guarantees that oscillator has started and stabilized.

Mar. 2005 Ver 0.2

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