MC80F0204 Datasheet, PDF(84/126 Page) List of Unclassifed Manufacturers

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MC80F0204 Datasheet, PDF (84/126 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

◁

MC80F0104/0204

Preliminary

18. INTERRUPTS

TheMC80F0104/0204 interrupt circuits consist of Inter-

rupt enable register (IENH, IENL), Interrupt request flags

of IRQH, IRQL, Priority circuit, and Master enable flag

(âIâ flag of PSW). Fifteen interrupt sources are provided.

The configuration of interrupt circuit is shown in Figure

18-1 and interrupt priority is shown in Table 18-1.

The External Interrupts INT0 ~ INT3 each can be transi-

tion-activated (1-to-0 or 0-to-1 transition) by selection

IEDS register.

The flags that actually generate these interrupts are bit

INT0IF, INT1IF, INT2IF and INT3IF in register IRQH.

When an external interrupt is generated, the generated flag

is cleared by the hardware when the service routine is vec-

tored to only if the interrupt was transition-activated.

The Timer 0 ~ Timer 3 Interrupts are generated by T0IF,

T1IF, T2IF and T3IF which is set by a match in their re-

spective timer/counter register.

The Basic Interval Timer Interrupt is generated by BITIF

which is set by an overflow in the timer register.

The AD converter Interrupt is generated by ADCIF which

is set by finishing the analog to digital conversion.

The Watchdog timer is generated by WDTIF and WTIF

which is set by a match in Watchdog timer register.

INT0

INT1

INT2

INT3

UART Rx

UART Tx

Serial

Communication

Timer 0

Timer 1

Timer 2

Timer 3

A/D Converter

Watchdog Timer

BIT

Internal bus line

IRQH

[0ECH]

INT0IF

INT1IF

INT2IF

INT3IF

UARTRIF

UARTTIF

SIOIF

IRQL

[0EDH]

T0IF

T1IF

T2IF

T3IF

[0EAH]

IENH

Interrupt Enable

I-flag is in PSW, it is cleared by âDIâ, set by

âEIâ instruction. When it goes interrupt service,

I-flag is cleared by hardware, thus any other

interrupt are inhibited. When interrupt service is

completed by âRETIâ instruction, I-flag is set to

â1â by hardware.

Release STOP/SLEEP

I-flag

Interrupt Master

Enable Flag

Interrupt

Vector

Address

Generator

To CPU

ADCIF

WDTIF

BITIF

[0EBH]

IENL

Interrupt Enable

Internal bus line

Figure 18-1 Block Diagram of Interrupt

Mar. 2005 Ver 0.2

▷