MC80F0204 Datasheet, PDF (78/126 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0104/0204
Preliminary
Asynchronous serial interface status register (ASISR)
When a receive error occurs during UART mode, this reg-
ister indicates the type of error. ASISR can be read by an 8
bit memory manipulation instruction. The RESET input
sets ASISR to ----_-000B. Figure 16-4 shows the format
of ASISR..
ASISR
R
R
R
7
6
5
4
3
2
1
0
-
-
-
- ^{BTC- L} PE FE OVE
ADDRESS: 0E7_H
INITIAL VALUE: ---- -000_B
UART Parity Error Flag
0: No parity error
1: Parity error (Transmit data parity not matched)
UART Frame Error Flag
0: No Frame error
1: Framing error^Note1 (stop bit not detected)
UART Overrun Error Flag
0: No overrun error
1: Overrun error^Note2
(Next receive operation was completed before data was read
from receive buffer register (RXR))
Note 1. Even if a stop bit length is set to 2 bits by setting bit2(SL) in
ASIMR, stop bit detection during a recive operation only applies
to a stop bit length of 1bit.
2. Be sure to read the contents of the receive buffer register(RXR)
when an overrun error has occurred.
Until the contents of RXR are read, futher overrun errors will
occur when receiving data.
Figure 16-4 Asynchronous Serial Interface Status Register (ASISR) Format
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Mar. 2005 Ver 0.2