MC80F0204 Datasheet, PDF (41/126 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

Preliminary
MC80F0104/0204
10. CLOCK GENERATOR
As shown in Figure 10-1 , the clock generator produces the
basic clock pulses which provide the system clock to be
supplied to the CPU and the peripheral hardware. It con-
tains main-frequency clock oscillator. The system clock
operation can be easily obtained by attaching a crystal or a
ceramic resonator between the X_IN and X_OUT pin, respec-
tively. The system clock can also be obtained from the ex-
ternal oscillator. In this case, it is necessary to input a
external clock signal to the X_IN pin and open the X_OUT pin.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuit-
STOP
INOSC
Main OSC
Stop
INOSC
X_IN
X_OUT
OSC
ONP
f_XIN
Circuit Circuit
Int OSC
Circuit
INCLK
MUX
ry is through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the data sheet
must be observed.
To the peripheral block, the clock among the not-divided
original clock, clocks divided by 1, 2, 4,..., up to 4096 can
be provided. Peripheral clock is enabled or disabled by
STOP instruction. The peripheral clock is controlled by
clock control register (CKCTLR). See "11. BASIC IN-
TERVAL TIMER" on page 39 for details.
SLEEP
f_EX
Clock Pulse
Generator
(÷2)
Internal
system clock
INOSC
PRESCALER
INOSC (IN4MCLK/IN2MCLK/
IN4MCLKXO/IN2MCLKXO)
PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12
7~3 2~0
÷1 ÷2 ÷4 ÷8 ÷16
Configuration Option Register (20FF_H)
f_EX (Hz)
PS0
PS1
PS2
PS3
PS4
PS5
Frequency 4M
2M
1M
4M
period
250n 500n
1u
500K
2u
250K
4u
125K
8u
÷32 ÷64 ÷128 ÷256 ÷512 ÷1024 ÷2048 ÷4096
Peripheral clock
PS6
PS7
PS8
PS9
PS10
62.5K 31.25K 15.63K 7.183K 3.906K
16u
32u
64u 128u 256u
PS11 PS12
1.953K 976
512u 1.024m
Figure 10-1 Block Diagram of Clock Generator
10.1 Oscillation Circuit
X_IN and X_OUT are the input and output, respectively, a in-
verting amplifier which can be set for use as an on-chip os-
cillator, as shown in Figure 10-2 .
Xout
C1
C2
Xin
Vss
Figure 10-2 Oscillator Connections
Note: When using a system clock oscillator, carry out wiring in
the broken line area in Figure 10-2 to prevent any effects from wir-
ing capacities.
- Minimize the wiring length.
- Do not allow wiring to intersect with other signal conductors.
- Do not allow wiring to come near changing high current.
- Set the potential of the grounding position of the oscillator capac-
itor to that of VSS. Do not ground to any ground pattern where high
current is present.
- Do not fetch signals from the oscillator.
Mar. 2005 Ver 0.2
37