MC80F0204 Datasheet, PDF (90/126 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

MC80F0104/0204
Preliminary
18.4 External Interrupt
The external interrupt on INT0, INT1, INT2 and INT3 pins
are edge triggered depending on the edge selection register
IEDS (address 0EE_H) as shown in Figure 18-7 .
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, and both edge.
01
INT0 pin
10
11
INT0IF
INT0 INTERRUPT
INT1 pin
01
10
INT1IF
INT1 INTERRUPT
11
INT2 pin
01
10
INT2IF
11
INT2 INTERRUPT
INT3 pin
01
10
INT3IF
11
2 22
IEDS
[0EEH]
2
Edge selection
Register
INT3 INTERRUPT
Figure 18-7 External Interrupt Block Diagram
INT0 ~ INT3 are multiplexed with general I/O ports (R11,
R12, R03, R00). To use as an external interrupt pin, the bit
of port selection register PSR0 should be set to “1” corre-
spondingly.
Example: To use as an INT0 and INT2
:
;**** Set external interrupt port as pull-up state.
LDM PU1,#0000_0101B
;
;**** Set port as an external interrupt port
LDM PSR0,#0000_0101B
;
;**** Set Falling-edge Detection
LDM IEDS,#0001_0001B
:
Response Time
The INT0 ~ INT3 edge are latched into INT0IF ~ INT3IF
at every machine cycle. The values are not actually polled
by the circuitry until the next machine cycle. If a request is
active and conditions are right for it to be acknowledged, a
hardware subroutine call to the requested service routine
will be the next instruction to be executed. The DIV itself
takes twelve cycles. Thus, a minimum of twelve complete
machine cycles elapse between activation of an external
interrupt request and the beginning of execution of the first
instruction of the service routine.
Figure 18-8 shows interrupt response timings.
max. 12 f_XIN
8 f_XIN
Interrupt Interrupt
goes latched
active
Interrupt
processing
Interrupt
routine
Figure 18-8 Interrupt Response Timing Diagram
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Mar. 2005 Ver 0.2