MC80F0204 Datasheet, PDF(43/126 Page) List of Unclassifed Manufacturers

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MC80F0204 Datasheet, PDF (43/126 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

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Preliminary

MC80F0104/0204

11. BASIC INTERVAL TIMER

The MC80F0104/0204 has one 8-bit Basic Interval Timer

that is free-run and can not stop. Block diagram is shown

in Figure 11-1 . In addition, the Basic Interval Timer gen-

erates the time base for watchdog timer counting. It also

provides a Basic interval timer interrupt (BITIF).

The 8-bit Basic interval timer register (BITR) is increased

every internal count pulse which is divided by prescaler.

Since prescaler has divided ratio by 8 to 1024, the count

rate is 1/8 to 1/1024 of the oscillator frequency. As the

count overflow from FFH to 00H, this overflow causes the

interrupt to be generated.

The Basic Interval Timer is controlled by the clock control

bit is set to â1â, the clock source of the BITR is changed to

the internal RC oscillation.

When write "1" to bit BTCL of CKCTLR, BITR register is

cleared to "0" and restart to count-up. The bit BTCL be-

comes "0" after one machine cycle by hardware.

If the STOP instruction executed after writing "1" to bit

RCWDT of CKCTLR, it goes into the internal RC oscillat-

ed watchdog timer mode. In this mode, all of the block is

halted except the internal RC oscillator, Basic Interval

Timer and Watchdog Timer. More detail informations are

explained in Power Saving Function. The bit WDTON de-

cides Watchdog Timer or the normal 7-bit timer.

Source clock can be selected by lower 3 bits of CKCTLR.

BITR and CKCTLR are located at same address, and ad-

dress 0F2H is read as a BITR, and written to CKCTLR.

Note: All control bits of Basic interval timer are in CKCTLR reg-

ister which is located at same address of BITR (address ECH). Ad-

dress ECH is read as BITR, written to CKCTLR. Therefore, the

CKCTLR can not be accessed by bit manipulation instruction.

XIN PIN

Internal RC OSC

RCWDT

Ã·8

Ã·16

Ã·32

Ã·64

Ã·128

Ã·256

Ã·512

Ã·1024

MUX

8-bit up-counter

1 source

clock

overflow

BITR

[0F2H]

clear

Select Input clock 3

BCK[2:0]

[0F2H]

Basic Interval Timer

clock control register

RCWDT

CKCTLR

BTCL

Read

Internal bus line

BITIF

Basic Interval

Timer Interrupt

To Watchdog timer (WDTCK)

Figure 11-1 Block Diagram of Basic Interval Timer

Mar. 2005 Ver 0.2

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