ACD82224 Datasheet, PDF (68/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

Read
0100XX01
A[7:0]
D[31:0]
C[7:0]
For response to a read operation, the Data field is a 4-octet value to indicate the content of the
register. For response to a write operation, the Data field is 32 bits of 0. If the data of register is
less than 24-bit, it is align to bit-0 of Data field.
The checksum value is an 8-bit value of exclusive-OR of all octets in the response frame,
starting from the Command octet.
The ARL will always check the command header to see if both the device type and the device ID
matches with its setting. If not, it ignores the command and does not generate any response to
this command.
5. REGISTER DESCRIPTION
The built-in ARL provides a number of registers for the CPU to access the address table.
Commands are sent to ARL by writing into the associated registers. Before the CPU can pass a
command to ARL, it must check the Result register (Register-11) for execution status of the
previous command. The CPU may need to retrieve the previous result before sending new
command. Then the CPU will write the new command parameters into the Data Registers, and
the command type into the Command Register. The ARL will then reset the Result Register to 0.
The Result register will indicate the completion of the command at the end of the execution.
Before the completion of the execution, any command written into the command register is
ignored by the ARL.
The registers accessible to the CPU are described by table-2:
Table-2: Register Description
Reg.
Register Name
0
DataReg0
1
DataReg1
2
DataReg2
3
DataReg3
4
DataReg4
5
DataReg5
6
DataReg6
7
DataReg7
8
AddrReg0
9
AddrReg1
10
CmdReg
11
RsltReg
12
CfgReg
13
IntSrcReg
14
IntMskReg
15
nLearnReg0
16
nLearnReg1
17
nLearnReg2
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
18
AgeTimeReg0
R/W
19
AgeTimeReg1
R/W
20
PosCfg
R/W
Size
8 Bit
8 Bit
8 Bit
8 Bit
8 Bit
8 Bit
8 Bit
8 Bit
8 Bit
8 Bit
8 Bit
5 Bit
8 Bit
8 Bit
8 Bit
8 Bit
8 Bit
8 Bit
8 Bit
8 Bit
3 Bit
Description
Byte 0 of data
Byte 1 of data
Byte 2 of data
Byte 3 of data
Byte 4 of data
Byte 5 of data
Byte 6 of data
Byte 7 of data
LSB of address value
MSB of address value
Command register
Result register
Configuration register
Interrupt source register
Interrupt mask register
Address learning disable register for port 0 – 7
Address learning disable register for port 8 – 15
Address learning disable register for port 16 –
23
LSB of aging period register
MSB of aging period register
Power On Strobe configuration register
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