ACD82224 Datasheet, PDF (44/77 Pages) List of Unclassifed Manufacturers – 24 Ports 10/100 Fast Ethernet Switch

P19TXEN
D24
P20CRS_DV A22
P20RXD0
B21
P20RXD1
C21
P20TXD0
B22
P20TXD1
D22
P20TXEN
A23
P21CRS_DV C20
P21RXD0
D18
P21RXD1
A19
P21TXD0
B20
P21TXD1
A20
P21TXEN
A21
P22CRS_DV B17
P22RXD0
C18
P22RXD1
A17
P22TXD0
B18
P22TXD1
A18
P22TXEN
C19
O
Transmit enable
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
I/O* Transmit data bit 0 (default low)
POS REG Bit-0 ZBT SRAM Read Timing Adjustment bit-0
I/O* Transmit data bit 1 (default low)
POS REG Bit-1: ZBT SRAM Read Timing Adjustment bit-1
I/O* Transmit enable (default high)
POS REG Bit-8: SRAM size selection bit-0
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
I/O* Transmit data bit 0 (default low)
POS REG Bit-2 ZBT SRAM Read Timing Adjustment bit-2
I/O* Transmit data bit 1 (default low)
POS REG Bit-3: ZBT SRAM Read Timing Adjustment bit-3
I/O* Transmit enable (default low)
POS REG Bit-9: SRAM size selection bit-1
I
Carrier Sense/Receive data valid
I
Receive data bit 0
I
Receive data bit 1
O
Transmit data bit 0
O
Transmit data bit 1
O
Transmit enable
MII Interface (Port 23)
Pin Name
Location
P23CRS
D08
P23RXDV
B15
P23RXCLK A15
P23RXERR C16
P23RXD0
A16
P23RXD1
C17
P23RXD2
B16
P23RXD3
D17
P23COL
C10
P23TXEN
D13
P23TXCLK D15
P23TXD0
C13
P23TXD1
D12
P23TXD2
C11
P23TXD3
D10
I/O
Description
I
Carrier sense (Shared with RMII P23CRS_DV)
I
Receive data valid
I
Receive clock (25/2.5 MHz)
I
Receive error
I
Receive data bit 0(Shared with RMII P23RXD0)
I
Receive data bit 1(Shared with RMII P23RXD1)
I
Receive data bit 2
I
Receive data bit 3
I
Collision indication
I/O* Transmit data valid (Shared with RMII P23TXEN)
POS REG Bit-22: RMII TX’s data is driven on falling edge/rising
edge (default high). Suggest pull-low with 4.7K resister.
I
Transmit clock (25/2.5 MHz)
I/O* Transmit data bit 0 (Shared with RMII P23TXD0)
CLKADJ REG Bit-0: ARL Clock Timing Adjustment bit-0
(default low).
I/O* Transmit data bit 1(Shared with RMII P23TXD1)
CLKADJ REG Bit-1: ARL Clock Timing Adjustment bit-1
(default low).
I/O* Transmit data bit 2
CLKADJ REG Bit-2: ARL Clock Timing Adjustment bit-2
(default high).
I/O* Transmit data bit 3
CLKADJ REG Bit-3: ARL Clock Timing Adjustment bit-3
(default high).
PHY Management Interface Signals
Pin Name
Location
I/O
Description
MDC
AD04
O
PHY management clock (1.25MHz)
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